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sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 1 version 1. 5 sn8p27 35 users manual version 1. 5 sn8p2735 sn8p2734 SN8P2733 sn8p2732 s s o o n n i i x x 8 8 - - b b i i t t m m i i c c r r o o - - c c o o n n t t r r o o l l l l e e r r sonix reserves the right to make change without further notice to any products herein to improve reliability, function or de sign . sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. sonix products are not designed, intended, or a uthorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the f ailure of the sonix product could create a situation where persona l injury or death may occur. should buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix and its officers, employees, subsidiaries, affiliates and distributors harmless against all c laims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part.
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 2 version 1. 5 amendent history version date description ver 0.1 dec . 200 8 first issue. ver 0. 2 mar . 200 9 major modification: 1. ihrc frequency is modified to 16mhz and related sections. 2. fcpu is modified to fhosc/2~fhosc/16 and related sections. 3. otp programming pin chapter. ver 1.0 sep. 2009 1. add sn8p2734/2733/2732 items , programming pin table and package information . 2. fix typing error. 3. modify ide version to m2ide_v120. ver 1.1 apr. 2011 1. u pdate pwm1/2 clock source description are fhosc, fcpu. 2. modify sn8p2734/33/32 pack a ge type at pin assignment . 3. add sn8p2734/33/32 to ? electrical characteristic description. 4. add development tool description. 5. modify marking definition contents ver 1.2 sep. 2011 1. m odify electrical characte rics chapter lvd range. 2. adjust chapter sequence. ver 1.3 oct. 2011 1. modify electrical characterics chapter operating temperature from 0~70 to - 10~70 . 2. modify lvd _l voltage from 2.0 to 1.8 and others . ver 1. 4 sep . 2012 modify electrical characterics chapter operating temperature from - 10~70 to - 20~85 and others. ver 1. 5 jan . 201 3 modify regis ter name : cm 0m >> cmp0m. cm 1 m >> cmp 1 m. cm 2 m >> cmp 2 m.
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 3 version 1. 5 table of content amendent history ................................ ................................ ................................ ................................ 2 1 1 1 product overview ................................ ................................ ................................ ......................... 7 1.1 features ................................ ................................ ................................ ................................ ........ 7 1.2 system block diagram ................................ ................................ ................................ .......... 8 1.3 pin assignment ................................ ................................ ................................ ........................... 9 1.4 pin descriptions ................................ ................................ ................................ ....................... 11 1.5 pin circuit diagrams ................................ ................................ ................................ ............. 13 2 2 2 central processor un it (cpu) ................................ ................................ .............................. 15 2.1 program memory (rom) ................................ ................................ ................................ ....... 15 2.1.1 reset vector (0000h) ................................ ................................ ................................ ...... 16 2.1.2 interrupt vector (0008h) ................................ ................................ ............................. 17 2.1.3 look - up table description ................................ ................................ ........................ 19 2.1.4 jump table description ................................ ................................ ............................... 21 2.1.5 checksum calculation ................................ ................................ ............................... 23 2.2 data memory (ram) ................................ ................................ ................................ ................ 24 2.2.1 system register ................................ ................................ ................................ .............. 25 2.2.1.1 system register table ................................ ................................ ............................ 25 2.2.1.2 system register description ................................ ................................ ............... 25 2.2.1.3 bit definition of system register ................................ ................................ ....... 26 2.2.2 accumulator ................................ ................................ ................................ ................... 28 2.2.3 program flag ................................ ................................ ................................ ................... 29 2.2.4 program counter ................................ ................................ ................................ ........... 30 2.2.5 h, l registers ................................ ................................ ................................ ..................... 33 2.2.6 y, z registers ................................ ................................ ................................ ..................... 34 2.2.7 r register ................................ ................................ ................................ ........................... 34 2.3 addressing mode ................................ ................................ ................................ .................... 35 2.3.1 immediate addressing mode ................................ ................................ .................... 35 2.3.2 directly addressing mode ................................ ................................ ....................... 35 2.3.3 indirectly addressing mode ................................ ................................ ................... 35 2.4 stac k operation ................................ ................................ ................................ ...................... 36 2.4.1 overview ................................ ................................ ................................ ............................. 36 2.4.2 stack registers ................................ ................................ ................................ ............... 37 2.4.3 stack operation example ................................ ................................ .......................... 38 2.5 code option table ................................ ................................ ................................ .................. 39 2.5.1 fcpu code option ................................ ................................ ................................ ...................... 40 2.5.2 reset_pin code option ................................ ................................ ................................ .............. 40 2.5.3 security code option ................................ ................................ ................................ ................. 40 2.5.4 noise filter code option ................................ ................................ ................................ ........... 40 3 3 3 reset ................................ ................................ ................................ ................................ ..................... 41 3.1 overview ................................ ................................ ................................ ................................ ..... 41 3.2 power on reset ................................ ................................ ................................ ......................... 42 3.3 watchdog reset ................................ ................................ ................................ ...................... 42 3.4 brown out reset ................................ ................................ ................................ ..................... 43 3.4.1 the system operating voltage ................................ ................................ .............. 44 3.4.2 low voltage detector (lvd) ................................ ................................ ................... 44 3.4.3 brown out reset improvement ................................ ................................ ............... 46 3.5 ex ternal reset ................................ ................................ ................................ ........................ 47 3.6 external reset circuit ................................ ................................ ................................ ....... 47
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 4 version 1. 5 3.6.1 simply rc reset circuit ................................ ................................ ................................ .......... 47 3.6.2 diode & rc reset circuit ................................ ................................ ................................ ........ 48 3.6.3 zener diode reset circuit ................................ ................................ ................................ ........ 48 3.6.4 voltage bias reset circuit ................................ ................................ ................................ ....... 49 3.6.5 external reset ic ................................ ................................ ................................ ...................... 49 4 4 4 system clock ................................ ................................ ................................ ................................ .. 50 4.1 overview ................................ ................................ ................................ ................................ ..... 50 4.2 f cpu (instruction cycle) ................................ ................................ ................................ ...... 50 4.3 noise filter ................................ ................................ ................................ ................................ 51 4.4 system high - speed c lock ................................ ................................ ................................ .... 51 4.4.1 high_clk code option ................................ ................................ ................................ ... 51 4.4.2 internal high - speed oscillator rc type (ihrc) ................................ ............. 51 4.4.3 external high - speed oscillator ................................ ................................ ........... 51 4.4.4 external oscillator application circuit ................................ ....................... 52 4.5 system low - speed clock ................................ ................................ ................................ ..... 53 4.6 oscm register ................................ ................................ ................................ ........................... 54 4.7 system clock measurement ................................ ................................ ............................. 54 4.8 system clock timing ................................ ................................ ................................ ............. 55 5 5 5 system operation mod e ................................ ................................ ................................ ........... 58 5.1 overview ................................ ................................ ................................ ................................ ..... 58 5.2 normal mode ................................ ................................ ................................ ............................ 59 5.3 slow mode ................................ ................................ ................................ ................................ .. 59 5.4 power down mdoe ................................ ................................ ................................ .................. 59 5.5 green mode ................................ ................................ ................................ ................................ 60 5.6 operating mode control macro ................................ ................................ .................... 61 5.7 wakeup ................................ ................................ ................................ ................................ ......... 62 5.7.1 overview ................................ ................................ ................................ ............................. 62 5.7.2 wakeup time ................................ ................................ ................................ ...................... 62 5.7.3 p1w wakeup control register ................................ ................................ ................ 63 6 6 6 interrupt ................................ ................................ ................................ ................................ ........... 64 6.1 overview ................................ ................................ ................................ ................................ ..... 64 6.2 inten interrupt enable register ................................ ................................ ................... 65 6.3 intrq interrupt request register ................................ ................................ ................ 66 6.4 gie global interrupt operation ................................ ................................ .................... 67 6.5 push, pop rout ine ................................ ................................ ................................ ..................... 68 6.6 external interrupt operation (int0~int2) ................................ ................................ 69 6.7 t0 interrupt operation ................................ ................................ ................................ ........ 70 6.8 tc0 interrupt operation ................................ ................................ ................................ ..... 71 6.9 t1 interrupt operation ................................ ................................ ................................ ........ 72 6.10 adc interrupt operation ................................ ................................ ................................ ... 73 6.11 comparator interrupt operation (cmp0~cmp2) ................................ ...................... 74 6.12 multi - interrupt operation ................................ ................................ ............................... 76 7 7 7 i/o port ................................ ................................ ................................ ................................ ................ 77 7.1 overview ................................ ................................ ................................ ................................ ..... 77 7.2 i/o port mode ................................ ................................ ................................ ............................. 78 7.3 i/ o pull up register ................................ ................................ ................................ ................ 79 7.4 i/o port data register ................................ ................................ ................................ .......... 80 7.5 port 4 adc share pin ................................ ................................ ................................ ............... 81 8 8 8 timers ................................ ................................ ................................ ................................ .................. 84 8.1 watchdog timer ................................ ................................ ................................ ...................... 84 8.2 t0 8 - bit basic timer ................................ ................................ ................................ ........................ 86 8.2.1 overview ................................ ................................ ................................ ............................. 86
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 5 version 1. 5 8.2.2 t0 timer operation ................................ ................................ ................................ .................. 87 8.2.3 t0m mode register ................................ ................................ ................................ ......... 88 8.2.4 t0c counting register ................................ ................................ ................................ . 88 8.2.5 t0 timer operation explame ................................ ................................ ..................... 89 8.3 tc0 8 - bit timer/counter ................................ ................................ ................................ ....... 90 8.3.1 overview ................................ ................................ ................................ ............................. 90 8.3.2 tc0 timer operation ................................ ................................ ................................ ...... 91 8.3.3 tc0m mode register ................................ ................................ ................................ ....... 92 8.3.4 tc0c counting register ................................ ................................ .............................. 93 8.3.5 tc0r auto - reload register ................................ ................................ ....................... 94 8.3.6 tc0 event counter ................................ ................................ ................................ ......... 95 8.3.7 tc0 buzzer output ................................ ................................ ................................ .......... 95 8.3.8 pulse width modulation (pwm) ................................ ................................ .............. 96 8.3.9 tc0 timer operation explame ................................ ................................ .................. 98 8.4 t1 16 - bit timer/counter ................................ ................................ ................................ ...... 100 8.4.1 overview ................................ ................................ ................................ ........................... 100 8.4.2 t1 timer operation ................................ ................................ ................................ ....... 101 8.4.3 t1m mode register ................................ ................................ ................................ ....... 102 8.4.4 t1ch, t1cl 16 - bit counting registers ................................ ................................ .... 103 8.4.5 t1 cpature timer ................................ ................................ ................................ ........... 104 8.4.6 t1 timer operation explame ................................ ................................ ................... 106 9 9 9 multi - purpose pulse width modulation (pwm1) ................................ .................... 107 9.1 overview ................................ ................................ ................................ ................................ ... 107 9.2 pwm1 common operation ................................ ................................ ................................ .. 108 9.3 inverse pwm1 output with dead - band function ................................ .................. 109 9.4 pwm synchronous trigger function ................................ ................................ ......... 110 9.5 pwm1 mode register ................................ ................................ ................................ ............ 111 9.6 pwm1 duty register ................................ ................................ ................................ ............. 113 9.7 pwm1 operation explame ................................ ................................ ................................ .. 114 1 1 1 0 0 0 6 - channel pulse width modulation (pwm2) ................................ .......................... 116 10.1 overview ................................ ................................ ................................ ................................ ... 116 10.2 pwm2 common operation ................................ ................................ ................................ .. 117 10.3 pwm2 mode register ................................ ................................ ................................ ............ 118 10.4 pwm2 channel selection register ................................ ................................ .............. 119 10.5 pwm2 duty register ................................ ................................ ................................ ............. 120 10.6 pwm2 operation explame ................................ ................................ ................................ .. 121 1 1 1 1 1 1 8 channel analog to digital converter (adc) ................................ ................... 122 11.1 overview ................................ ................................ ................................ ................................ ... 122 11.2 adc mode register ................................ ................................ ................................ ............... 123 11.3 adc data buffer registers ................................ ................................ .............................. 124 11.4 adc operation description and notic ................................ ................................ ....... 125 11.4.1 adc signal format ................................ ................................ ................................ ...... 125 11.4.2 adc converting time ................................ ................................ ................................ .. 125 11.4.3 adc pin configuration ................................ ................................ .............................. 126 11.4.4 adc operation examlpe ................................ ................................ ............................ 127 11.5 adc application circuit ................................ ................................ ................................ ......... 129 1 1 1 2 2 2 rail to rail analog comparaotr ................................ ................................ ............... 130 12.1 overview ................................ ................................ ................................ ................................ ... 130 12.2 comparator mode register ................................ ................................ ............................ 132 12.3 comparator application notice ................................ ................................ .................. 135 1 1 1 3 3 3 rail to rail op ampl ifer ................................ ................................ ................................ .... 136 13.1 overview ................................ ................................ ................................ ................................ ... 136
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 6 version 1. 5 13.2 op amp register ................................ ................................ ................................ ...................... 137 1 1 1 4 4 4 instruction table ................................ ................................ ................................ ................. 138 1 1 1 5 5 5 electrical character istic ................................ ................................ ............................ 139 15.1 absolute maximu m rating ................................ ................................ .............................. 139 15.2 electrical characteristic ................................ ................................ ............................. 139 15.3 characteristic graphs ................................ ................................ ................................ ..... 141 1 1 1 6 6 6 development tool ................................ ................................ ................................ ................ 142 16.1 sn8p2735 ev - kit ................................ ................................ ................................ .......................... 142 16.2 ice and ev - kit application notic ................................ ................................ .................... 143 1 1 1 7 7 7 otp programming pin ................................ ................................ ................................ ........... 145 17.1 writer transition board socket pin assignment ................................ ............... 145 17.2 programming pin mapping: ................................ ................................ ............................... 146 1 1 1 8 8 8 marking definition ................................ ................................ ................................ ............... 148 18.1 introduction ................................ ................................ ................................ .......................... 148 18.2 marking indetification system ................................ ................................ .................... 148 18.3 marking example ................................ ................................ ................................ ................. 149 18.4 datecode system ................................ ................................ ................................ .................. 150 1 1 1 9 9 9 package information ................................ ................................ ................................ ......... 151 19.1 p - dip 32 pin ................................ ................................ ................................ ................................ .. 151 19.2 lqfp 32 pin ................................ ................................ ................................ ................................ .. 152 19.3 sk - dip 28 pin ................................ ................................ ................................ ............................... 153 19.4 sop 28 pin ................................ ................................ ................................ ................................ ..... 154 19.5 sk - dip 24 pin ................................ ................................ ................................ ............................... 155 19.6 sop 24 pin ................................ ................................ ................................ ................................ ..... 156 19.7 p - dip 20 pin ................................ ................................ ................................ ................................ .. 157 19.8 sop 20 pin ................................ ................................ ................................ ................................ ..... 158
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 7 version 1. 5 1 1 1 product overview 1.1 features ? features selection table chip rom ram stack timer ? i i/o pwm adc op - amp comp arator wake - up pin no. package t0 tc0 t1 8bit 8~ 12 bit sn8p2735 6 k*16 256 8 v v v 30 1 7 8 - ch 3 3 14 pdip32/ lqfp32 sn8p2734 6 k*16 256 8 v v v 26 1 3 8 - ch 3 3 14 skdip28/ sop28 SN8P2733 6 k*16 256 8 v v v 22 1 2 8 - ch 2 2 11 skdip24/ sop24 sn8p2732 6 k*16 256 8 v v v 18 1 2 7 - ch 1 1 8 dip20/ sop20 ? memory configuration ? one 8 - bit basic timer. (t0). rom size: 6k * 16 bits. ? one 8 - bit timer with external event counter , ram size: 256 * 8 bits. buzzer and pwm. (tc0). ? one 16 - bit capture timer. ( t1). ? 8 levels stack buffer. ? 6 - channel 8/10/12 bits pwm. ? 1 - channel 8/10/12 bits pwm with dead - band and inverse output. ? 10 interrupt sources ? 8 - channel 12 - bit sar adc . 7 internal interrupts: t0, t1, tc0, adc, cm0, cm1, ? 3 - set rail - to - rail op - amp . cm2 ? 3 - set rail - to - rail comparator . 3 external interrupt: int0 , int1, int2 ? on chip watchdog timer and clock source is internal low clock rc type (16khz @3v, 32khz ? i/o pin configuration @5v). bi - directional: p0, p1, p4, p5 . wakeup: p0, p1 level change. ? four system clocks pull - up resisters: p0, p1, p4, p5. external high clock: rc type up to 10 mhz op - amp/ comparator pin s : p1.0~p1.7, p5.0 . external high clock: crystal type up to 16 mhz adc input pin: p4.0~p4.7. internal high clock: rc type 16 mhz internal low clock: rc type 16khz(3v), 32khz(5v) ? 3 - level lvd. reset system and power monitor. ? four operating modes normal mode: both high and low clock active ? fcpu (instruction cycle) slow mode: low c lock only fcpu = fosc/1, f o sc/2, fosc/4, fosc/8, fosc/16. sleep mode: both high and low clock stop green mode: periodical wakeup by timer ? powerful instructions instruction?s length is one word. ? package (chip form support) most of instruc tions are one cycle only. pdip 32 pin all rom area jmp /call instruction. lqfp 32 pin all rom area lookup table function (movc).
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 8 version 1. 5 1.2 system block diagram i n t e r r u p t c o n t r o l e x t e r n a l h i g h o s c . a c c i n t e r n a l l o w r c t i m i n g g e n e r a t o r r a m s y s t e m r e g i s t e r s 3 - l e v e l l v d ( l o w v o l t a g e d e t e c t o r ) w a t c h d o g t i m e r t i m e r & c o u n t e r p 0 p 5 p 1 6 - c h p w m 1 - c h p w m + i n v e r s e a l u p c f l a g s i r o t p r o m p w m 1 , p w m 1 n p 4 i n t e r n a l h i g h r c 1 6 m h z c o m p a r a t o r 0 c o m p a r a t o r 1 1 2 - b i t a d c a i n 0 ~ a i n 7 c o m p a r a t o r 2 o p a 0 o p a 1 o p a 2 c m 0 n , c m 0 p , c m 0 o c m 1 n , c m 1 p , c m 1 o c m 2 n , c m 2 p . c m 2 o o p 0 n , o p 0 p , o p 0 o o p 1 n , o p 1 p , o p 1 o o p 2 n , o p 2 p . o p 2 o p w m 2 1 ~ p w m 2 6 p w m , b u z z e r p w m 0 , b z 0
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 9 version 1. 5 1.3 pin assignment sn8p27 35p ( pdi p 32 pins ) v ss 1 u 32 v dd xin/p0. 5 2 31 p4.7/ain7 xout/p0. 4 3 30 p4.6/ain6 rst/vpp/p0. 3 4 29 p4.5/ain 5 p0.2/int2/pwm 1n 5 28 p4.4/ain4 p0.1/ int1/pwm 1 6 2 7 p4.3/ain3 p0.0/int0/pwm1t 7 26 p4.2/ain2 p5.7/pwm 26 8 25 p4.1/ain1 p5.6/pwm 25 9 24 p4.0/ain0/avrefh p5.5/pwm 24 10 23 p1.0/cm 2 n /op2n p5.4/bz 0 /pwm0 11 22 p1.1/cm 2 p /op2p p5.3 /pwm 23 12 21 p1.2/cm 2 o /op2o p5.2 /pwm 22 13 20 p1.3/cm 1 n / op1n p5.1 /pwm 21 14 19 p1.4/cm 1 p /op1p p5.0/cm 0o/op0o 15 18 p1.5/cm 1 o /op1o p1.7/cm0p/op0p 16 17 p1.6/cm0n/op0n sn8p2735p sn8p27 35f ( lqf p 32 pins ) rst/vpp/p0. 3 xout/p0. 4 xin/p0. 5 v ss v dd p4.7/ain7 p4.6/ain6 p4.5/ain 5 o 32 31 30 29 28 27 26 25 p0.2/int2/pwm 1n 1 24 p4.4/ain4 p0.1/int1/pwm 1 2 23 p4.3/ain3 p0.0/int0/pwm1t 3 22 p4.2/ain2 p5.7/pwm 26 4 sn8p2735f 21 p4.1/ain1 p5.6/pwm 25 5 20 p4.0/ain0/avrefh p5.5/pwm 24 6 19 p1.0/cm 2 n /op2n p5.4/bz 0 /p wm0 7 18 p1.1/cm 2 p /op2p p5.3 /pwm 23 8 17 p1.2/cm 2 o /op2o 9 10 11 12 13 14 15 16 p5.2 /pwm 22 p5.1 /pwm 21 p5.0/cm 0o/op0o p1.7/cm0p/op0p p1.6/cm0n/op0n p1.5/cm 1 o /op1o p1.4/cm 1 p /op1p p1.3/cm 1 n /op1n
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 10 version 1. 5 sn8p27 34p ( sk - di p 28 pins ) sn8p27 34 s ( so p 28 pins ) v ss 1 u 28 v dd xin/p0. 5 2 27 p4.7/ain7 xout/p0. 4 3 26 p4.6/ain6 rst/vpp/p0. 3 4 25 p4.5/ain 5 p0.2/int2/pwm 1n 5 24 p4.4/ain4 p0.1/int1/pwm 1 6 23 p4.3/ain3 p0.0/int0/pwm1t 7 22 p4.2/ain2 p5.4/bz 0 /pwm0 8 21 p4.1/ain1 p5.2 /pwm 22 9 20 p4.0/ain0/avrefh p5.1 /pwm 21 10 19 p1.0/cm 2 n /op2n p5.0/cm 0o/op0o 11 18 p1.1/cm 2 p /op2p p1.7/cm0p/op0p 12 17 p1.2/cm 2 o /op2o p1.6/cm0n/op0n 13 16 p1.3/cm 1 n /op1n p1.5/cm 1 o /op1o 14 15 p1.4/cm 1 p /op1p sn8p273 4 sn8p27 33k ( sk - di p 24 pins ) sn8p27 33s ( so p 24 pins ) v ss 1 u 24 v dd xin/p0. 5 2 23 p4.7/ain7 xout/p0. 4 3 22 p4.6/ain6 rst/vpp/p0. 3 4 21 p4.5/ain 5 p0.2/int2/pwm 1n 5 20 p4.4/ain4 p0.1/int1/pwm 1 6 18 p4.3/ain3 p0.0/int0/pwm1t 7 19 p4.2/ain2 p5.4/bz 0 /pwm0 8 17 p4.1/ain1 p5.1 /pwm 2 1 9 16 p4.0/ain0/avrefh p5.0/cm 0o/op0o 10 15 p1.3/cm 1 n /op1n p1.7/cm0p/op0p 11 14 p1.4/cm 1 p /op1p p1.6/cm0n/op0n 12 13 p1.5/cm 1 o /op1o sn8p273 3 sn8p27 32p ( pdi p 20 pins ) sn8p27 32s ( so p 20 pins ) v ss 1 u 20 v dd xin/p0. 5 2 19 p4.6/ain6 xout/p0. 4 3 18 p4.5/ain 5 rst/vpp/p0. 3 4 17 p4.4/ain4 p0.2/int2/pwm 1n 5 16 p4.3/ain3 p0.1/int1/pwm 1 6 15 p4.2/ain2 p0.0/int0/pwm1t 7 14 p4.1/ain1 p5.4/bz 0 /pwm0 8 13 p4.0/ain0/avrefh p5.1 /pwm 21 9 12 p1.6/cm0n/op0n p5.0/cm 0o/op0o 10 11 p1.7/cm0p/op0p sn 8p273 2
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 11 version 1. 5 1.4 pin descriptions pin name type description vdd, vss p power supply input pins for digital and analog circuit. p0.3/rst/vpp i, p rst: system external reset input pin. schmitt trigger structure, active low, normal stay to high. vpp: ot p 12.3v power input pin in programming mode. p0.3: input only pin with schmitt trigger structure and no pull - up resistor. xin/p0.5 i/o xin: oscillator input pin while external oscillator enable (crystal and rc). p0.5: bi - direction pin. schmitt tri gger structure as input mode. built - in pull - up resisters. xout/p0.4 i/o xout: oscillator output pin while external crystal enable. p0.4: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. p0.0/int0/pwm1t i/o p0.0 : bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. int0: external interrupt 0 input pin. tc0 event counter input pin. pwm1t: pwm1 external trigger source. p0.1/int1/pwm1 i/o p0.1: bi - direction pin. schmit t trigger structure as input mode. built - in pull - up resisters. int1: external interrupt 1 input pin. pwm1: 4 - phase speed - up pwm output pin. p0.2/int2/pwm1n i/o p0.2: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resi sters. int2: external interrupt 2 input pin. pwm1n: pwm1 negative output pin. p1.0/cm2n/op2n i/o p1.0: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm2n: the negative input pin of comparator. op2n : the negative input pin of op amp. p1.1/cm2p/op2p i/o p1.1: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm2p: the positive input pin of comparator. op2p: the positive input pin of op amp. p1.2/cm2o/op 2o i/o p1.2: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm2o: the output pin of comparator. op2o: the output pin of op amp. p1.3/cm1n/op1n i/o p1.3: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm1n: the negative input pin of comparator. op1n: the negative input pin of op amp. p1.4/cm1p/op1p i/o p1.4: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm1p: the po sitive input pin of comparator. op1p: the positive input pin of op amp. p1.5/cm1o/op1o i/o p1.5: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm1o: the output pin of comparator. op1o: the output pin of op amp. p1.6/cm0n/op0n i/o p1.6: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm0n: the negative input pin of comparator. op0n: the negative input pin of op amp. p1.7/cm0p/op0p i/o p1.7: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. cm0p: the positive input pin of comparator. op0p: the positive input pin of op amp. p5.0/cm0o/op0o i/o p5.0: bi - direction pin. schmitt trigger structure as input mode. bui lt - in pull - up resisters. cm0o: the output pin of comparator. op0o: the output pin of op amp. p5.1/pwm21 i/o p5.1: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. pwm21: channel 1 of 4 - phase speed - up pwm 2 output pin. p5.2/ pwm22 i/o p5.2: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. pwm22: channel 2 of 4 - phase speed - up pwm2 output pin. p5.3/ pwm23 i/o p5.3: bi - direction pin. schmitt trigger structure as in put mode. built - in pull - up resisters. pwm23: channel 3 of 4 - phase speed - up pwm2 output pin. p5.4/ bz0 /pwm0 i/o p5.4: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters.
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 12 version 1. 5 bz0 : programmable buzzer output pin from tc 0/2 signal. pwm0: programmable pwm output pin from tc0. p5.5/pwm24 i/o p5.5: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. pwm24: channel 4 of 4 - phase speed - up pwm2 output pin. p5.6/pwm25 i/o p5.6: bi - di rection pin. schmitt trigger structure as input mode. built - in pull - up resisters. pwm25: channel 5 of 4 - phase speed - up pwm2 output pin. p5.7/pwm26 i/o p5.7: bi - direction pin. schmitt trigger structure as input mode. built - in pull - up resisters. pw m26: channel 6 of 4 - phase speed - up pwm2 output pin. p4.0/ain0/avrefh i/o p4.0: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain0: adc analog input pin. avrefh: adc reference high voltage input pin. p4.1/ain1 i/o p 4.1: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain1: adc analog input pin. p4.2/ain2 i/o p4.2: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain2: adc analog input pin. p4.3/ain3 i /o p4.3: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain3: adc analog input pin. p4.4/ain4 i/o p4.4: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain4: adc analog input pin. p4.5/ai n5 i/o p4.5: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain5: adc analog input pin. p4.6/ain6 i/o p4.6: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain6: adc analog input pin. p4. 7/ain7 i/o p4.7: bi - direction pin. no schmitt trigger structure. built - in pull - up resisters. ain7: adc analog input pin. refer to adc section.
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 13 version 1. 5 1.5 pin circuit diagrams ? p 0.3 structure: ? p0.4, p0.5 structure: ? p0.0~p0.2, p5.1~p5.7 structure: ? p4.0 structure : ? p4.1~p4.7 structure : p i n e x t . r e s e t c o d e o p t i o n i / o i n p u t b u s r e s e t p u l l - u p r e s i s t o r o u t p u t l a t c h p i n p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m h i g h _ c l k c o d e o p t i o n o s c i l l a t o r d r i v e r p u l l - u p r e s i s t o r o u t p u t l a t c h p i n p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m a v r e f h a v r e f h p i n g c h s p 4 c o n a d c i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m a d e n b p i n a d e n b , g c h s p 4 c o n a d c i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 14 version 1. 5 ? p1.0~p1.7, p5.0 op - amp shared pins structure : ? p1.0~p 1.7, p5.0 comparator shared pins structure : comparator negative pin: comparator positive pin: comparator output pin: p i n o p n e n o p - a m p t e r m i n a l p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m p i n c m n e n c o m p a r a t o r n e g a t i v e i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m p i n c m n e n c o m p a r a t o r p o s i t i v e i n p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m c m n r e f p i n c m n e n c o m p a r a t o r o u t p u t p u l l - u p r e s i s t o r o u t p u t l a t c h p n u r p n m i / o i n p u t b u s i / o o u t p u t b u s p n m c m n o e n
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 15 version 1. 5 2 2 2 central processor unit (cpu) 2.1 program memory (rom) ? 6k word s rom rom 0000h reset vector user reset vector jump to user start address 0001h general purpose area . . 0007h 0008h interrupt vector user interrupt vector 0009h general purpose area user program . . 000fh 0010h 0011h . . . . . 17 f ch end of user program 17 f dh reserved 17 f eh 17 f fh the rom includes reset vector, interrupt vector, general purpose area and reserved area. the reset vector is program beginning address. the interrupt vector is the head of interrupt service routine when any interrupt occurring. the general purpose area is main program area including main loop, sub - routines and data table.
sn8p 2735 adc, op - amp, comparator 8 - b it m icro - c ontroller sonix technology co., ltd page 16 version 1. 5 2.1.1 reset vector (0000h) a one - word vector address area is used to execute system reset . ? power on reset (nt0=1, npd=0). ? watchdog reset (nt0=0, npd=0). ? external reset (nt0=1, npd=1). after power on reset , external reset or watchdog timer overflow reset , then the chip will restart the program from address 0000h and all system registers wil l be set as default values. it is easy to know reset status from nt0, npd flags of pflag register. the following example shows the way to define the reset vector in the program memory. ? example : defining reset vector org 0 ; 0000h jmp start ; jump to u ser program address. org 10h start: ; 00 10 h, the head of user program. endp ; end of program
sn8p27 35 adc, op - amp, co mparator 8 - bit micro - controller sonix technology co., ltd page 17 version 1. 5 2.1.2 interrupt vector (0008h) a 1 - word vector address area is used to execute interrupt request. if an y interrupt service executes, the program counter (pc) value is stored in stack buffer and jump to 0008h of program memory to execute the vectored interrupt. users have to define the interrupt vector . the following example shows the way to define the inter rupt vector in the program memory. ? note: push , pop instructions save and load acc/pflag without ( nt0, npd). push/pop buffer is a unique buffer and only one level. ? example: defining interrupt vector. the interrupt service routine is following or g 8. .code org 0 ; 0000h jmp start ; jump to user program address. org 8 ; interrupt vector. push ; save acc and pflag register to buffers. pop ; load acc and pflag register from buffers. reti ; end of interrupt se rvice routine
sn8p27 35 adc, op - amp, co mparator 8 - bit micro - controller sonix technology co., ltd page 18 version 1. 5 ? example: defining interrupt vector. the interrupt service routine is following user program . .code org 0 ; 0000h jmp start ; jump to user program address. org 8 ; interrupt vector. jmp my_ irq ; 0008h, jump to interrupt service routine address. org 10 h start: ; 0010h, the head of user program. my _ i r q : ;the head of interrupt service routine. push ; save acc and pflag register to buffers. pop ; load acc and pflag register from buffers. reti ; end of interrupt service routi ne. ? note: it is easy to understand the rules of sonix program from demo programs given above. these points are as following: 1. the address 0000h is a jmp instruction to make the program starts from the beginning . 2. th e address 0008h is interrupt vector. 3. user s program is a loop routine for main purpose application.
sn8p27 35 adc, op - amp, co mparator 8 - bit micro - controller sonix technology co., ltd page 19 version 1. 5 2.1.3 look - up table description in the rom?s data lookup function, y register is pointed to middle byte address ( bit 8~bit 15 ) and z register is pointed to low byte address ( bit 0~bit 7 ) of rom. after movc instruction executed, the low - byte data will be stored in acc and high - byte data stored in r register. ? example: to look up the rom data located table1. b0mov y, #table1$m ; to set lookup table1?s midd ; to set lookup table1?s low address. ; increment the index address for next address . incms z ; z+1 jmp @f ; z is n ot overflow . incms y ; z overflow (ffh ? 00), ? y= y+1 nop ; ; @@: movc ; to lookup data, r = 51h, acc = 05h. ? note : the y register will not increase automatically when z register cross es boundary from 0xff to 0x00. therefore, user must be take care such situation to avoid loo k - up table errors. if z register is overflow, y register must be added one. the following inc_yz macro shows a simple method to process y and z registers automatica lly. ? example: inc_yz macro . inc_yz macro incms z ; z+1 jmp @f ; not overflow incms y ; y+1 nop ; not overflow @@: endm
sn8p27 35 adc, op - amp, co mparator 8 - bit micro - controller sonix technology co., ltd page 20 version 1. 5 ? example: modify above example by inc_yz macro . b0mov y, #table1$m ; to set lookup table 1?s middle address ; to set lookup table1?s low address. inc_yz ; increment the index address for next address . ; @@: movc ; to lookup data, r = 51h, acc = 05h. be careful if carry happen. ? example: increase y and z register by b0a dd/add instruction . b0mov y, #table1$m ; to set lookup table?s middle address. ; to set lookup table?s low address. b0mov a, buf ; z = z + buf. b0add z, a b0bts1 fc ; check the carry flag. jmp get data ; fc = 0 incms y ; fc = 1. y+1. nop getdata: ; movc ; to lookup data. if buf = 0, data is 0x0035 ; if buf = 1, data is 0x5105 ; if buf = 2, data is 0x2012
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 21 version 1. 5 2.1.4 jump table description the jump table operation is one of mu l ti - address jumping function . add low - byte program counter (pcl) and acc value to get one new pcl. if pcl is overflow after pcl+acc, pch adds one automatic ally. the new program counter (pc) points to a series jump instructions as a listing table. i t is easy to make a mu l ti - jump program depends on the value of the accumulator (a) . ? note: pch only support pc up counting result and doesn t support pc down coun ting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl C acc, pch keeps value and not change. ? example: jump table. org 0x0100 ; the jump table is from the head of the rom boundary b0add pcl, a ; pcl = pcl + acc, pch + 1 when pcl overflow occurs . jmp a0point ; acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, jump to a2point jmp a3point ; acc = 3, jump to a3point sonix provides a macro for safe jump table fun ction. this macro will check the rom boundary and move the jump table to the right position automatically. the side effect of this macro maybe wastes some rom size. ? example: if jump table crosses over rom boundary will cause errors. @jmp_a macro val if (($+1) !& 0xff00) !!= (($+(val)) !& 0xff00) jmp ($ | 0xff) org ($ | 0xff) endif b0 add pcl, a endm ? note: val is the number of the jump table listing number.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 22 version 1. 5 ? example: @jmp_a application in sonix macro file called macro3.h . b0mov a, buf0 ; @jmp_a macro will adjust the jump table routine begin from next ram boundary (0x0100). ? example: @jmp_a operation. ; before compiling program. rom address b0mov a, buf0 ; ; after compiling program. rom address b0mov a, buf0 ;
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 23 version 1. 5 2.1.5 checksum calculation the last rom address are reserved area. user should avoid these addresses (last address) when calculate the checksum value. ? example: the demo program shows how to calculated checksum from 00h to the end of us ers code . mov a,#end_user_code$l b0mov end_addr1, a ; s ave low end address to end_addr1 mov a,#end_user_code$m b0mov end_addr2, a ; s ave middle end address to end_addr2 clr y ; s et y to 00h clr z ; s et z to 00h @@: movc b0bset fc ; c lear c f lag add data1, a ; a dd a to data1 mov a, r adc data2, a ; a dd r to data2 jmp end_check ; c heck if the yz address = the end of code aaa: incms z ; z=z+1 jmp @b ; if z != 00h calculate to next address jmp y_add_1 ; i f z = 00h i ncrease y end_check: mov a, end_addr1 cmprs a, z ; c heck if z = low end address jmp aaa ; i f not jump to checksum calculate mov a, end_addr2 cmprs a, y ; i f yes, check if y = middle end address jmp aaa ; i f not jump to checksum calculate jmp checksum_end ; i f yes checksum calculated is done. y_add_1: incms y ; i ncrease y nop jmp @b ; j ump to checksum calculate checksum_end: end_user_code: ; label of program end
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 24 version 1. 5 2.2 data memory (ram) ? 256 x 8 - bit ram address ram l ocation bank 0 000h general p urpose a rea ram bank 0 system r egister 080h~0ffh of bank 0 store system registers (128 bytes). bank 1 100 h general p urpose a rea ram ban k 1 ? ram is controlled by rbank register. when rbank = 0, the program controls bank 0 ram directly. when rbank = 1, t he program controls bank 1 ram directly. under one bank condition and need to access the other bank ram, setup the rbank register is necessary. sonix provides bank 0 type instructions (e.g. b0mov, b0add, b0bts1, b0bset ) to control bank 0 ram in non - zero ram bank condition directly. ? example: access bank 0 ram in bank 1 condition. move bank 0 ram (wk00) value to bank 1 ram (wk01). ; bank 1 (rbank = 1) b0mov a , wk00 ; use bank 0 type instruction to access bank 0 ram. mov wk01,a ? note: for mult i - bank ram program, it is not easy to control ram bank selection. users have to take care the rbank condition very carefully , especially for interrupt service routine. the system wont switch ram bank to bank 0, so these controls must be through program. i t is a good to use bank 0 type instruction to process the situations .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 25 version 1. 5 2.2.1 system register 2.2.1.1 system register table 0 1 2 3 4 5 6 7 8 9 a b c d e f 8 l h r z y - pflag rbank - - - - - - - - 9 pw1n m - - pw1m pw2m pw2c hs pw1rh pw1rl pw2rh pw2rl - - cm p 0m cm p 1m cm p 2m opm a t1m t1cl t1ch - - - - - - - - - - - p4con - b - adm adb adr adt - - - p0m - - - - - - pedge c p1w p1m - - p4m p5m - - intrq inten oscm - wdtr tc0r pcl pch d p0 p1 - - p4 p5 - - t0m t0c tc0m tc0c - - - stkp e p0ur p1ur - - p4ur p5ur @h l @yz - - - - - - - - f stk 7l stk 7h stk 6l stk 6h stk 5l st k5h stk 4l stk 4h stk3 l stk3 h stk2 l stk2 h stk1 l stk1 h stk0 l stk0 h 2.2.1.2 system register description h, l = working, @ hl addressing register. y, z = working, @yz and rom addressing register. r = working register and rom look - up data buffer. pflag = s pecial flag register. rbank = ram bank select register . pw1nm = inverse pwm 1 mode register. pw1m = pwm 1 mode register. pw2m = pwm 2 mode register. pw2chs = pwm 2 output channel select register. pw1rh, l = pwm 1 reload buffers. pw2rh, l = pwm 2 reload buffers. cm p 0m = comparator 0 mode register. cm p 1m = comparator 1 mode register. cm p 2m = comparator 2 mode register. opm = op amp 0~2 mode register. t1m = t1 mode register. t1ch, l = t1 counting registers. p 4con = p4 configuration register. adm = adc mode register. adb = adc data buffer. adr = adc resolution select register. adt = adc offset calibration register. pedge = p0.0, p0.1, p0.2 edge direction register. intrq = interrupt request register. inten = interrupt enable register. wdtr = watchdog timer clear register. pnm = port n input/output mode register. pn = port n data buffer. pnur = port n pull - up resister control register. oscm = oscillator mode register. pch, pcl = program counter. t0m = t0 m ode register. t0c = t0 counting register. t c0 m = t c0 mode register. t c0 c = tc 0 counting register. tc0r = tc0 auto - reload data buffer. @ hl = ram hl indirect addressing index pointer. @yz = ram yz indirect addressing index pointer. stkp = stack pointer b uffer. stk0~stk 7 = stack 0 ~ stack 7 buffer.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 26 version 1. 5 2.2.1.3 bit definition of system register address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w remarks 080h lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 r/w l 081h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit 0 r/w h 082h rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 r/w r 083h zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 r/w z 084h ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 r/w y 086h nt0 npd lvd36 lvd24 c dc z r/w pflag 087h rbnks0 r/w rbank 090h pw1nen pw1d2 pw1d1 pw1d0 pw1den pw1nv r/w pw1nm 093h pw1en pw1rate2 pw1rate1 pw1rate0p pw1cks pw1ln1 pw1ln0 pw1s r/w pw1m 094h pw2en pw2rate2 pw2rate1 pw2rate0 pw2cks pw2ln1 pw2ln0 r/w pw2m 095h pw2ch6 pw2ch5 pw2ch4 pw2ch3 pw2ch2 pw2ch1 r/w pw2chs 096h pw1gs pw1gen pw1gd pw1r11 pw1r10 pw1r9 pw1r8 r/w pw1rh 097h pw1r7 pw1r6 pw1r5 pw1r4 pw1r3 pw1r2 pw1r1 pw1r0 w pw1rl 098h pw2r11 pw2r10 pw2r9 pw2r8 r/w pw2rh 099h pw2r7 pw2r6 pw2r5 pw2r4 pw2r3 pw2r2 pw2r1 pw2r0 w pw2rl 09ch cm0en cm0ien cm0irq cm0oen cm0ref cm0out cm0g1 cm0g0 r/w cm p 0m 09dh cm1en cm1ien cm1irq cm1oen cm1ref cm1out cm1g1 cm1g0 r/w cm p 1m 09eh cm2en cm2ien cm2irq cm2oen cm2ref cm2out cm2g1 cm2g0 r/w cm p 2m 09fh op2en op1en op0en r/w opm 0a0h t1enb t1rate2 t1rate1 t1rate0 cptcks cptstart cptg1 cptg0 r/w t1m 0a1h t1cl7 t1cl6 t1cl5 t1cl4 t1cl3 t1cl2 t1cl1 t1cl0 r/w t1cl 0a2h t1ch7 t1ch6 t1ch5 t1ch4 t1ch3 t1ch2 t1ch1 t1ch0 r/w t1ch 0aeh p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 w p4con 0b1h adenb ads eoc gchs avrefh chs2 chs1 chs0 r/w adm 0b2h adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 r adb 0b3h adcks1 adlen adcks0 adb3 adb2 adb1 adb0 r/w adr 0b4h adts1 adts0 adt4 adt3 adt2 adt1 adt0 r/w adt 0b8h p05m p04m - p02m p01m p00m r/w p0m 0bfh p02g 1 p02g0 p01g1 p01g0 p00g1 p00g0 r/w pedge 0c0h p17w p16w p15w p14w p13w p12w p11w p10w w p1w 0c1h p17m p16m p15m p14m p13m p12m p11m p10m r/w p1m 0c4h p47m p46m p45m p44m p43m p42m p41m p40m r/w p4m 0c5h p57m p56m p55m p54m p53m p52m p51m p50m r/w p5m 0c8h adcirq t1irq tc0irq t0irq p02irq p01irq p00irq r/w intrq 0c9h adcien t1ien tc0ien t0ien p02ien p01ien p00ien r/w inten 0cah cpum1 cpum0 clkmd stphx r/w oscm 0cch wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 w wdtr 0cdh tc0r7 tc0r6 tc0r5 tc0r4 tc0r3 tc0r2 tc0r1 tc0r0 w tc0r 0ceh pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 r/w pcl 0cfh pc12 pc11 pc10 pc9 pc8 r/w pch 0d0h p05 p04 p03 p02 p01 p00 r/w p0 0d1h p17 p16 p15 p14 p13 p12 p11 p10 r/w p1 0d4h p47 p46 p45 p44 p43 p42 p41 p40 r/w p4 0d5 h p57 p56 p55 p54 p53 p52 p51 p50 r/w p5 0d8h t0enb t0rate2 t0rate1 t0rate0 t0tb r/w t0m 0d9h t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0c0 r/w t0c 0dah tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out r/w tc0m 0dbh tc0c7 tc0c6 tc0c5 tc0c4 t c0c3 tc0c2 tc0c1 tc0c0 r/w tc0c 0dfh gie stkpb2 stkpb1 stkpb0 r/w stkp 0e0h p05r p04r - p02r p01r p00r w p0ur 0e1h p17r p16r p15r p14r p13r p12r p11r p10r w p1ur 0e4h p47r p46r p45r p44r p43r p42r p41r p40r w p4ur 0e5h p57r p56r p55r p54r p53r p 52r p51r p50r w p5ur 0e6h @hl7 @hl6 @hl5 @hl4 @hl3 @hl2 @hl1 @hl0 r/w @hl 0e7h @yz7 @yz6 @yz5 @yz4 @yz3 @yz2 @yz1 @yz0 r/w @yz 0f0h s7pc7 s7pc6 s7pc5 s7pc4 s7pc3 s7pc2 s7pc1 s7pc0 r/w stk7l 0f1h s7pc12 s7pc11 s7pc10 s7pc9 s7pc8 r/w stk7h 0f2h s6pc7 s6pc6 s6pc5 s6pc4 s6pc3 s6pc2 s6pc1 s6pc0 r/w stk6l 0f3h s6pc12 s6pc11 s6pc10 s6pc9 s6pc8 r/w stk6h 0f4h s5pc7 s5pc6 s5pc5 s5pc4 s5pc3 s5pc2 s5pc1 s5pc0 r/w stk5l 0f5h s5pc12 s5pc11 s5pc10 s5pc9 s5pc8 r/w stk5h 0f6h s4pc7 s4pc6 s4pc5 s4pc4 s4pc3 s4pc2 s4pc1 s4pc0 r/w stk4l 0f7h s4pc12 s4pc11 s4pc10 s4pc9 s4pc8 r/w stk4h 0f8h s3pc7 s3pc6 s3pc5 s3pc4 s3pc3 s3pc2 s3pc1 s3pc0 r/w stk3l 0f9h s3pc12 s3pc11 s3pc10 s3pc9 s3pc8 r/w stk3h 0fah s2pc7 s2pc6 s2pc5 s2pc4 s2pc3 s2pc2 s2pc1 s2pc0 r/w s tk2l
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 27 version 1. 5 0fbh s2pc12 s2pc11 s2pc10 s2pc9 s2pc8 r/w stk2h 0fch s1pc7 s1pc6 s1pc5 s1pc4 s1pc3 s1pc2 s1pc1 s1pc0 r/w stk1l 0fdh s1pc12 s1pc11 s1pc10 s1pc9 s1pc8 r/w stk1h 0feh s0pc7 s0pc6 s0pc5 s0pc4 s0pc3 s0pc2 s0pc1 s0pc0 r/w stk0l 0ffh s0pc12 s0p c11 s0pc10 s0pc9 s0pc8 r/w stk0h ? note: 1. to avoid system error, make sure to put all the 0 and 1 as it indicates in the above table . 2. all of register name s had been declared in sn8asm assembler. 3. one - bit name had been declared in sn8asm assembler with f prefix code. 4. b0bset, b0bclr, bset, bclr instructions are only available to the r/w registers .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 28 version 1. 5 2.2.2 accumulator the acc is an 8 - bit data register responsible for transferring or manipulating data between alu and data memory. if the result of o perating is zero (z) or there is carry (c or dc) occurrence, then these flags will be set to pflag register. acc is not in data memory (ram), so acc can?t be access by b0mov instruction during the instant addressing mode. ? example: read and write acc va lue. ; read acc data and store in buf data memory . mov buf, a ; write a immediate data into acc . mov a, #0fh ; write acc data from buf data memory . mov a, buf ; or b0 mov a, buf the system doesn?t store acc and pflag v alue when interrupt executed. acc and pflag data must be saved to other data memories. push , pop save and load acc, pflag data into buffers. ? example: protect acc and working registers . int_service: push ; save acc and pflag to buffers. pop ; l oad acc and pflag from buffers. reti ; exit interrupt service vector
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 29 version 1. 5 2.2.3 program flag the pflag register contains the arithmetic status of alu operation, system reset status and lvd detecting status. nt0, npd bits indicate s ystem reset status including power on reset, lvd reset, reset by external pin active and watchdog reset. c, dc, z bits indicate the result status of alu operation. lvd24, lvd36 bits indicate lvd detecting power voltage status. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd lvd36 lvd24 - c dc z read/write r/w r/w r r - r/w r/w r/w after reset - - 0 0 - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd reset status 0 0 watch - dog time out 0 1 reserved 1 0 reset by lvd 1 1 reset by external reset pin bit 5 lvd36: lvd 3.6v operating flag and only support lvd code option is lvd_h. 0 = inactive (vdd > 3.6v). 1 = active (vdd Q 3.6v). bit 4 lvd24: lvd 2.4v operating flag and only support lvd code option is lvd_m. 0 = inactive (vdd > 2.4v). 1 = active (vdd Q 2.4v). bit 2 c: carry flag 1 = a ddition with carry , subtraction without borrowing , rotation with shifting out logic 1 , comparison result R 0. 0 = a ddition without carry , subtraction with borrowing signal , rotation with shiftin g out logic 0 , comparison result < 0. bit 1 dc: decimal carry flag 1 = a ddition with carry from low nibble , subtraction without borrow from high nibble. 0 = a ddition without carry from low nibble , subtraction with borrow from high nibble. bit 0 z: ze ro flag 1 = the result of an a rithmetic /logic/branch operation is zero . 0 = the result of an a rithmetic /logic/branch operation is not zero . ? note: refer to instruction set table for detailed information of c, dc and z flags.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 30 version 1. 5 2.2.4 program counter the pr ogram counter (pc) is a 1 3 - bit binary counter separated into the high - byte 5 and the low - byte 8 bits. this counter is responsible for pointing a location in order to fetch an instruction for kernel circuit. normally, the program counter is automatically in cremented with each instruction during program execution. besides, it can be replaced with specific address by executing call or jmp instruction. when jmp or call instruction is executed, the destination address will be inserted to bit 0 ~ bit 12. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pc - - - pc12 pc11 pc10 pc9 pc8 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 after reset - - - 0 0 0 0 0 0 0 0 0 0 0 0 0 pch pcl ? one address skipping there are nine instructions (cmprs, incs, incms, decs, decms, bts0, bts1, b0bts0, b0bts1) with one address skipping function. if the result of these instructions is true, the pc will add 2 steps to skip next instruction. if the condition of bit test instruction is true, the pc will add 2 steps to skip next instruction. b0bts1 fc ; to skip, if carry_flag = 1 jmp c0step ; else jump to c0step. b0bts 0 f z ; to skip, if zero flag = 0. jmp c1ste p ; else jump to c1step. if the acc is equal to the immediate data or memory, the pc will add 2 steps to skip next instruction. cmprs a, #12h ; to skip, if acc = 12h. jmp c0step ; else jump to c0step.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 31 version 1. 5 if the destination increased by 1 , which results overflow of 0xff to 0x00, the pc will add 2 steps to skip next instruction. incs instruction: incs buf0 jmp c0step ; jump to c0step if acc is not zero. c0step: nop incms inst ruction: incms buf0 jmp c0step ; jump to c0step if buf0 is not zero. c0step: nop if the destination decreased by 1 , which results underflow of 0x0 1 to 0x 00 , the pc will add 2 steps to skip next instruction. decs instruction: decs b uf0 jmp c0step ; jump to c0step if acc is not zero. c0step: nop decms instruction: decms buf0 jmp c0step ; jump to c0step if buf0 is not zero. c0step: nop
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 32 version 1. 5 ? multi - address jumping users can jump a round the multi - ad dress by either jmp instruction or add m, a instruction (m = pcl) to activate multi - address jumping function. program counter supports add m,a , adc m,a and b0add m,a instructions for carry to pch when pcl overflow automatically. for jump table or oth ers applications, users can calculate pc value by the three instructions and don?t care pcl overflow problem. ? note : pch only support pc up counting result and doesn t support pc down counting. when pcl is carry after pcl+acc, pch adds one automatically. if pcl borrow after pcl C acc, pch keeps value and not change. ? example: if pc = 0323h (pch = 03h , pcl = 23h) ; pc = 0323h mov a, #28h b0mov pcl, a ; jump to address 0328h ; pc = 0328h mov a, #00h b0mov pcl, a ; jump to addr ess 0300h ? example: if pc = 0323h (pch = 03h , pcl = 23h) ; pc = 0323h b0add pcl, a ; pcl = pcl + acc, the pch cannot be changed. jmp a0point ; if acc = 0, jump to a0point jmp a1point ; acc = 1, jump to a1point jmp a2point ; acc = 2, ju mp to a2point jmp a3point ; acc = 3, jump to a3point
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 33 version 1. 5 2.2.5 h, l registers the h and l registers are the 8 - bit buffers. there are two major functions of these registers. ? c an be used as general working registers ? c an be used as ram data pointe rs with @hl register 081h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 h hbit7 hbit6 hbit5 hbit4 hbit3 hbit2 hbit1 hbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - 080h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l lbit7 lbit6 lbit5 lbit4 lbit3 lbit2 lbit1 lbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - ? example: if want to read a data from ram address 20h of bank_0, it can use indirectly addressing mode to access data as following. b0mov h, #00h ; to set ram bank 0 for h register b0mov l, #20h ; to set location 20h for l register b0mov a, @hl ; to read a data into acc ? example: clear general - purpose data memory area of bank 0 using @hl register. clr h ; h = 0, bank 0 b0mo v l, #07fh ; l = 7fh, the last address of the data memory area clr_hl_buf: clr @hl ; clear @hl to be zero decms l ; l C
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 34 version 1. 5 2.2.6 y, z registers the y and z registers are the 8 - bit buffers. there are three major functions of these registers. ? c an be used as general working registers ? c an be used as ram data pointers with @yz register ? c an be used as rom data pointer with the movc instruction for look - up table 084h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 y ybit7 ybit6 ybit5 ybit4 ybit3 ybit2 ybit1 ybit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - 083h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 z zbit7 zbit6 zbit5 zbit4 zbit3 zbit2 zbit1 zbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset - - - - - - - - ? example: uses y, z register as the data pointer to access data in the ram address 025h of b ank0. b0mov y, #00h ; to set ram bank 0 for y register b0mov z, #25h ; to set location 25h for z register b0mov a, @yz ; to read a data into acc ? example: uses the y, z register as data pointer to clear the ram data. b0mov y, #0 ; y = 0, bank 0 b0mov z, #07fh ; z = 7fh, the last address of the data memory area clr_yz_buf: clr @yz ; clear @yz to be zero decms z ; z C 2.2.7 r register r register is an 8 - bit buffer. there are two major functions of the register. ? can be used as working register ? for store high - byte data of look - up table (movc instruction executed, the high - byte data o f specified rom address will be stored in r register and the low - byte data will be stored in acc). 082h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 r rbit7 rbit6 rbit5 rbit4 rbit3 rbit2 rbit1 rbit0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after r eset - - - - - - - - ? note: please refer to the look - up table description about r register look - up table application.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 35 version 1. 5 2.3 addressing mode 2.3.1 immediate addressing mode the immediate addressing mode uses an immediate data to set up the location in acc or specific ram. ? example: move the immediate data 12h to acc. mov a, #12h ; to set an immediate data 12h into acc. ? example: move the immediate data 12h to r register. b0mov r, #12h ; to set an immediate data 12h into r register. ? note: in immedia te addressing mode application, the specific ram must be 0x80~0x87 working register. 2.3.2 directly addressing mode the directly addressing mode moves the content of ram location in or out of acc. ? example: move 0x12 ram location data into acc. b0mov a , 12h ; to get a content of ram location 0x12 of bank 0 and save in acc. ? example: move acc data into 0x12 ram location. b0mov 12h, a ; to get a content of acc and save in ram location 12h of bank 0. 2.3.3 indirectly addressing mode the indirectly address ing mode is to access the memory by the data pointer registers (h/l, y/z). ? example: indirectly addressing mode with @hl register b0mov h, #0 ; to clear h register to access ram bank 0. b0mov l, #12h ; to set an immediate data 12h into l register. b0 mov a, @hl ; use data pointer @hl reads a data from ram location ; 012h into acc. ? example: indirectly addressing mode with @yz register b0mov y, #0 ; to clear y register to access ram bank 0. b0mov z, #12h ; to set an immediate data 12h into z register. b0mov a, @yz ; use data pointer @yz reads a data from ram location ; 012h into acc.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 36 version 1. 5 2.4 stack operation 2.4.1 overview the stack buffer has 8 - level. these buffers are designed to push and pop up program counter?s (pc) data when interrupt servi ce routine and call instruction are executed. the stkp register is a pointer designed to point active level in order to push or pop up data from stack buffer. the stknh and stknl are the stack buffer s to store program counter (pc) data. ret / reti call / interrupt stkp = 7 stkp = 6 stkp = 5 stkp = 4 stack level stk7h stk6h stk5h stk4h stack buffer high byte pch stkp stk7l stk6l stk5l stk4l stack buffer low byte pcl stkp stkp - 1 stkp + 1 stkp = 3 stkp = 2 stkp = 1 stkp = 0 stk3l stk2l stk1l stk0l stk3h stk2h stk1h stk0h
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 37 version 1. 5 2.4.2 stack registers the stack pointer (stkp) is a 3 - bit register to store the address used to access the stack buffer, 13 - bit data memory ( stknh and stknl ) set aside for temporary storage of stack addresses. the two stack operations are wr iting to the top of the stack (push) and reading from the top of stack (pop). push operation decrements the stkp and the pop operation incre ments each time. that makes the stkp always point to the top address of stack buffer and write the last program coun ter value (pc) into the stack buffer. the program counter (pc) value is stored in the stack buffer before a call instruction executed or during interrupt service routine. stack operation is a lifo type (last in and first out). the stack pointer (stkp) an d stack buffer (stknh and stknl) are located in the system register area bank 0. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit[2:0] stkp bn: stack pointer (n = 0 ~ 2) bit 7 gie: global interrupt control bit. 0 = d isable. 1 = e nable. please refer to the interrupt chapter. ? example: stack pointer (stkp) reset, we strongly recommended to clear the stack pointers in the beginning of the p rogram. mov a, #0000 0 111b b0mov stkp, a 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknh - - - snpc12 snpc11 snpc10 snpc9 snpc8 read/write - - - r/w r/w r/w r/w r/w after reset - - - 0 0 0 0 0 0f0h~0ffh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stknl snpc7 snpc6 snpc5 snpc4 snpc3 snpc2 snpc1 snpc0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 stkn = stknh , stknl (n = 7 ~ 0)
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 38 version 1. 5 2.4.3 stack operation example the two kinds of stack - save operations refer to the stack pointer (stkp) and write the content of program counter (pc) to the stack buffer are call instruction and interrupt service. under each condition, the stkp decre ases and points to the next available stack location. the stack buffer store s the program counter about the op - code address. the stack - save operation is as the following table. stack level stkp register stack buffer description stkpb 2 stkpb 1 stkpb0 high byte low byte 0 1 1 1 free free - 1 1 1 0 stk0h stk0l - 2 1 0 1 stk1h stk1l - 3 1 0 0 stk2h stk2l - 4 0 1 1 stk3h stk3l - 5 0 1 0 stk4h stk4l - 6 0 0 1 stk5h stk5l - 7 0 0 0 stk6h stk6l - 8 1 1 1 stk7h stk7l - > 8 1 1 0 - - stack over, error there are stack - restore operation s correspond to e ach push operation to re store the program counter (pc). the reti instruction uses for interrupt service routine. the ret instruction is for call instruction. when a pop operation occurs, the stkp is incre mented and points to the next free stack location. the stack buffer restores the last program counter (pc) to the program counter registers. the stack - restore operation is as the following table. stack level stkp register stack buffer description stkpb2 stkpb1 stkpb0 high byte low byte 8 1 1 1 stk7h stk7l - 7 0 0 0 stk6h stk 6l - 6 0 0 1 stk5h stk5l - 5 0 1 0 stk4h stk4l - 4 0 1 1 stk3h stk3l - 3 1 0 0 stk2h stk2l - 2 1 0 1 stk1h stk1l - 1 1 1 0 stk0h stk0l - 0 1 1 1 free free -
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 39 version 1. 5 2.5 code option table the code option is the system hardware configurations including osci llator type, noise filter option, watchdog timer operation, lvd option, reset pin option and otp rom security control. the code option items are as following table: code option content function description high_clk ihrc_16m high speed internal 16mhz rc. xin/xout pins are bi - direction gpio mode. ihrc_rtc high speed internal 16mhz rc. xin/xout pins are connected to external 32768hz crystal. rc low cost rc for external high clock oscillator . xin pin is connected to rc oscillator. xout pin is bi - directi on gpio mode. 32k x?tal 12m x?tal 4m x?tal notice: in fosc/ 1 , noise filter must be disabled. f h osc/2 instruction cycle is 2 oscillator clocks. notice: in fosc/2, noise filter must be disabled. f h osc/4 in struction cycle is 4 oscillator clocks. f h osc/8 instruction cycle is 8 oscillator clocks. f h osc/16 instruction cycle is 16 oscillator clocks. noise_filter enable enable noise filter and the fcpu is fosc/4~fosc/1 6 . disable disable noise filter and th e fcpu is fosc/ 2 ~fosc/1 6 . watch_dog always_on watchdog timer is always on enable even in power down and green mode. enable enable w atchdog timer. watchdog timer stops in power down mode and green mode. disable disable watch d og function . reset_pin res et enable external reset pin. p03 enable p0.3 input only without pull - up resister. security enable enable rom code security function . disable disable rom code security function . lvd lvd_l lvd will reset chip if vdd is below 1.8 v lvd_m lvd will rese t chip if vdd is below 1.8 v enable lvd24 bit of pflag register for 2.4v low voltage indicator. lvd_h lvd will reset chip if vdd is below 2.4v enable lvd36 bit of pflag register for 3.6v low voltage indicator. lvd_max lvd will reset chip if vdd is below 3.6v
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 40 version 1. 5 2.5.1 fcpu code option fcpu means instruction cycle of normal mode (high clock). in slow mode, the system clock source is internal low speed rc oscillator. the fcpu of slow mode isn ? t controlled by fcpu code option and fixed flosc/4 (16khz/4 @3v, 32khz /4 @5v). 2.5.2 reset_pin code option the reset pin is shared with general input only pin controlled by code option. ? reset : the reset pin is external reset function . w hen falling edge trigger occurring, the system will be reset. ? p03 : set reset pin to general i nput only pin (p0.3). the external reset function is disabled and the pin is input pin. 2.5.3 security code option security code option is otp rom protection. when enable security code option, the rom code is secured and not dumped complete rom contents. 2.5.4 noi se filter code option noise filter code option is a power noise filter manner to reduce noisy effect of system clock. if noise filter enable, fcpu is limited below fhosc/1 and fhosc/2. the fast fcpu rate is fhosc/4. if noise filter disable, the fhosc/1 and fhosc/2 options are released. in high noisy environment, enable noise filter, enable watchdog timer and select a good lvd level can make whole system work well and avoid error event occurrence.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 41 version 1. 5 3 3 3 reset 3.1 overview the system would be reset in three condit ions as following. ? power on reset ? watchdog reset ? brown out reset ? external reset (only supports external reset pin enable situation) when any reset condition occurs, all system registers keep initial status, program stops and program counter is cleared. after reset status released, the system boots up and program starts to execute from org 0. the nt0, npd flags indicate system reset status. the system can depend on nt0, npd status and go to different paths by program. 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd lvd36 lvd24 - c dc z read/write r/w r/w r r - r/w r/w r/w after reset - - 0 0 - 0 0 0 bit [7:6] nt0, npd: reset status flag. nt0 npd condition description 0 0 watchdog reset watchdog timer overflow. 0 1 reserved - 1 0 power on reset and lvd reset. power voltage is lower than lvd detecting level. 1 1 external reset external reset pin detect low level status. finishing any reset sequence needs some time. the system provides complete procedure s to make the power on re set successful. for different oscillator types, the reset time is different. that causes the vdd rise rate and start - up time of different oscillator is not fixed. rc type oscillator ? s start - up time is very short, but the crystal type is longer. under clien t terminal application, users have to take care the power on reset time for the master terminal requirement. the reset timing diagram is as following. vdd vss vdd vss watchdog normal run watchdog stop system normal run system stop lvd detect level external reset low detect external reset high detect watchdog overflow watchdog reset delay time external reset delay time power on delay time power external reset watchdog reset system status
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 42 version 1. 5 3.2 power on reset the power on reset depend no lvd operation for most pow er - up situations. the power supplying to system is a rising curve and needs some time to achieve the normal voltage. power on reset sequence is as following. ? power - up: system detects the power voltage up and waits for power stable. ? external reset (only ex ternal reset pin enable): system checks external reset pin status. if external reset pin is not high level, the system keeps reset status and waits external reset pin released. ? system initialization: all system registers is set as initial conditions and sy stem is ready. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. 3.3 watchdog reset watchdog reset is a system protection. in normal condit ion, system works well and clear s watchdog timer by program. under error condition, system is in unknown situation and watchdog can ? t be clear by program before watchdog timer overflow. watchdog timer overflow occurs and the system is reset. after watchdog reset, the system restarts and returns normal mode. watchdog reset sequence is as following. ? watchdog timer status: system checks watchdog timer overflow status. if watchdog timer overflow occurs, the system is reset. ? system initialization: all system re gisters is set as initial conditions and system is ready. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. watchdog timer application note is as following. ? before clearing watchdog timer, check i/o status and check ram contents can improve system error. ? don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. ? clearing watchdog ti mer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? note: please refer to the watchdog timer about watchdog timer detail information .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 43 version 1. 5 3.4 brown out reset the brown out reset is a power dropping condition. the power drops from normal voltage to low voltage by external factors (e.g. eft interference or external loading changed). the brown out reset would make the system not work well or executing program error. brown out reset diagram the power dropping might through the voltage range that ? s the system dead - band. the dead - band means the power range can?t offer the system minimum operation power requirement . the above diagram is a typical brown out reset diag ram . there is a serious noise under the vdd, and vdd voltage drops very deep. there is a dotted line to separate the system working area. the above area is the system work well area. the below area is the system work error area called dead - band. v1 does n?t touch the below area and not effect the system operation. but the v2 and v3 is under the below area and may induce the system error occurrence. let system under dead - band includes some condition s. dc application: the power source of dc application is usu ally using battery. when low battery condition and mcu drive any loading, the power drops and keeps in dead - band. under the situation, the power won?t drop deeper and not touch the system reset voltage. that make s the system under dead - band. ac applicatio n: in ac power application, the dc power is regulated from ac power source. this kind of power usually couples with ac noise that makes the dc power dirty. or the external loading is very heavy, e.g. driving motor. the loading operating induces noise and o verlaps with the dc power. vdd drops by the noise, and the system works under unstable power situation. the power on duration and power down duration are longer in ac application. the system power on sequence protects the power on successful, but the power down situation is like dc low battery condition. when turn off the ac power, the vdd drops slowly and through the dead - band for a while. vdd vss v1 v2 v3 system work well area system work error area
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 44 version 1. 5 3.4.1 the system operating voltage to improve the brown out reset needs to know the system minimum operating voltage whi ch is depend on the system executing rate and power level. different system executing rates have different system minimum operating voltage. the electrical characteristic section shows the system voltage to executing rate relationship . normally the system operation voltage area is higher than the system reset voltage to vdd, and the reset voltage is decided by lvd detect level. the system minimum operating voltage rises when the system executing rate upper even higher than sys tem reset voltage. the dead - band definition is the system minimum operating voltage above the system reset voltage. 3.4.2 low voltage detector (lvd) the lvd (low voltage detector) is built - in sonix 8 - bit mcu to be brown out reset protection. when the vdd drops and is below lvd detect voltage, the lvd would be triggered, and the system is reset. the lvd detect level is different by each mcu. the lvd voltage level is a point of voltage and not easy to cover all dead - band range. usin g lvd to improve brown out reset is depend on application requirement and environment . if the power variation is very deep, violent and trigger the lvd, the lvd can be the protection. if the power variation can touch the lvd detect level and make system wo rk error, the lvd can ? t be the protection and need to other reset methods. more detail lvd information is in the electrical characteristic section. the lvd is three levels design ( 1.8 v/2.4v/3.6v) and cont rolled by lvd code option. the 1.8 v lvd is always e nable for power on reset and brown out reset. the 2.4v lvd includes lvd reset function and flag function to indicate vdd status function . the 3.6v includes flag function to indicate vdd status. lvd flag function can be an easy low battery detector . lvd24, lvd36 flags indicate vdd voltage level. for low battery detect application, only checking lvd24, lvd36 status to be battery status. this is a cheap and easy solution. vdd (v) system rate (fcpu) system mini. operating voltage. system reset voltage. dead-band area normal operating area reset area vdd vss system normal run system stop lvd detect voltage power on delay time power system status power is below lvd detect voltage and system reset.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 45 version 1. 5 086h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pflag nt0 npd lvd36 lvd24 - c dc z read/write r/w r/w r r - r/w r/w r/w after reset - - 0 0 - 0 0 0 bit 5 lvd36: lvd 3.6v operating flag and only support lvd code option is lvd_h. 0 = inactive (vdd > 3.6v). 1 = active (vdd Q 3.6v). bit 4 lvd24: lvd 2.4v operating flag and only support lvd code option is lvd_m. 0 = inactive (vdd > 2.4v). 1 = active (vdd Q 2.4v). lvd lvd code option lvd_l lvd_m lvd_h lvd_max 1.8 v reset available available available available 2 .4v flag - available - - 2.4v reset - - available - 3.6v flag - - available - 3.6v reset - - - available lvd_l if vdd < 1.8 v, system will be reset. disable lvd24 and lvd36 bit of pflag register. lvd_m if vdd < 1.8 v, system will be reset. enable lvd24 bit of pflag register. if vdd > 2.4v, lvd24 is 0. if vdd Q 2.4v, lvd24 flag is 1. disable lvd36 bit of pflag register. lvd_h if vdd < 2.4v, system will be reset. enable lvd24 bit of pflag register. if vdd > 2.4v, lvd24 is 0. if vdd Q 2.4v, lvd24 flag is 1. enable lvd36 bit of pflag register. if vdd > 3.6v, lvd36 is 0. if vdd Q 3.6v, lvd36 flag is 1. lvd_max if vdd < 3.6v, system will be reset. ? note: 1. after any lvd reset, lvd24, lvd36 flags are cleared. 2. the voltage level of lvd 2.4v or 3.6v is for design reference only. don t use the lvd indicator as pr ecision vdd measurement.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 46 version 1. 5 3.4.3 brown out reset improvement how to improve the brown reset condition? there are some methods to improve brown out reset as following. ? lvd reset ? watchdog reset ? reduce the system executing rate ? external reset circuit. (zener di ode reset circuit, voltage bias reset circuit, external reset ic) ? note: 1. the zener diode reset circuit , voltage bias reset circuit and external reset ic can completely improve the brown out reset, dc low battery and ac slow power down condition s. 2. for ac power application and enhance eft performance, the system clock is 4mhz/4 (1 mips) and use external reset ( zener diode reset circuit , voltage bias reset circuit , external reset ic ). the structure can improve noise effective and get good eft c haracteristic. watchdog reset: the watchdog timer is a protection to make sure the system executes well. normally the watchdog timer would be clear at one point of program. don?t clear the watchdog timer in several addresses. the system executes norma lly and the watchdog won ? t reset system. when the system is under dead - band and the execution error, the watchdog timer can?t be clear by program. the watchdog is continuously counting until overflow occurrence. the overflow signal of watchdog timer trigge rs the system to reset, and the system return to normal mode after reset sequence. this method also can improve brown out reset condition and make sure the system to return normal mode. if the system reset by watchdog and the power is still in dead - band, the system reset sequence won?t be successful and the system stays in reset status until the power return to normal range. watchdog timer application note is as following. reduce the system executing rate: if the system rate is fast and the dead - band exis ts, to reduce the system executing rate can improve the dead - band. the lower system rate is with lower minimum operating voltage. select the power voltage that ? s no dead - band issue and find out the mapping system rate. adjust the system rate to the value a nd the system exits the dead - band issue. this way needs to modify whole program timing to fit the application requirement. external reset circuit: the external reset methods also can improve brown out reset and is the complete solution. there are three ex ternal reset circuits to improve brown out reset including zener diode reset circuit , voltage bias reset circuit and external reset ic . these three reset structures use external reset signal and control to make sure the mcu be reset under power dropp ing and under dead - band. the external reset information is describe d in the next section.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 47 version 1. 5 3.5 external reset external reset function is controlled by reset_pin code option. set the code option as reset option to enable external reset function. external r eset pin is schmitt trigger structure and low level active. the system is running when reset pin is high level voltage input. the reset pin receives the low voltage and the system is reset. the external reset operation actives in power on and normal runnin g mode. during system power - up, the external reset pin must be high level input, or the system keeps in reset status. external reset sequence is as following. ? external reset (only external reset pin enable): system checks external reset pin status. if ext ernal reset pin is not high level, the system keeps reset status and waits external reset pin released. ? system initialization: all system registers is set as initial conditions and system is ready. ? oscillator warm up: oscillator operation is successfully and supply to system clock. ? program executing: power on sequence is finished and program executes from org 0. the external reset can reset the system during power on duration, and good external reset circuit can protect the system to avoid working at un usual power condition, e.g. brown out reset in ac power application 3.6 external reset circu it 3.6.1 simply rc reset circuit this is the basic reset circuit, and only includes r1 and c1. the rc circuit operation makes a slow rising si gnal into reset pin as power up. the reset signal is slower than vdd power up timing, and system occurs a power on signal from the timing difference. ? note: the reset circuit is no any protection against unusual power or brown out reset. mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf r2 100 ohm
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 48 version 1. 5 3.6.2 diode & rc reset circuit this is the better reset circuit. the r1 and c1 circuit operation is like the simply reset circuit to make a power on signal. the reset circuit has a simply protection against unusual power. the diode offers a po wer positive path to conduct higher power to vdd. it is can make reset pin voltage level to synchronize with vdd voltage. the structure can improve slight brown out reset condition. ? note: the r2 100 ohm resistor of simply reset circuit and diode & rc reset circuit is necessary to limit any current flowing into reset pin from external capacitor c in the e vent of reset pin breakdown due to electrostatic discharge (esd) or electrical over - stress (eos). 3.6.3 zener diode reset circuit the zener diode reset circuit is a simple low voltage detector and can improve brown out reset condition completely . use zener voltage to be the active level. when vdd voltage level is above vz + 0.7v , the c terminal of the pnp transistor outputs h igh voltage and mcu operates normally. when vdd is below vz + 0.7v , the c terminal of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by zener specification . select the right zener voltage to conform the a pplication. mcu vdd vss vcc gnd r s t r1 47k ohm c1 0.1uf diode r2 100 ohm mcu vdd vss vcc gnd r s t r1 33k ohm r3 40k ohm r2 10k ohm vz q1 e c b
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 49 version 1. 5 3.6.4 voltage bias reset circuit the voltage bias reset circuit is a low cost voltage detector and can improve brown out reset condition completely . the operating voltage is not accurate as zener diode reset circuit. us e r1, r2 bias voltage to be the active level. when vdd voltage level is above or equal to 0.7v x (r1 + r2) / r1 , the c terminal of the pnp transistor outputs high voltage and mcu operates normally. when vdd is below 0.7v x (r1 + r2) / r1 , the c termina l of the pnp transistor outputs low voltage and mcu is in reset mode. decide the reset detect voltage by r1, r2 resistances. select the right r1, r2 value to conform the application. in the circuit diagram condition, the mcu ? s reset pin level varies with vdd voltage variation , and the differential voltage is 0.7v. if the vdd drops and the voltage lower than reset pin detect level, the system would be reset. if want to make the reset active earlier, set the r2 > r1 and the cap between vdd and c terminal vol tage is larger than 0.7v. the external reset circuit is with a stable current through r1 and r2. for power consumption issue application, e.g. dc power system, the current must be consider ed to whole system power consumption. ? note: under unstable power c ondition as brown out reset, zener diode rest circuit and voltage bias reset circuit can protects system no any error occurrence as power dropping. when power drops below the reset detect voltage, the system reset would be triggered, and then system ex ecutes reset sequence. that makes sure the system work well under unstable power situation. 3.6.5 external reset ic the external reset circuit also use external reset ic to enhance mcu reset performance. this is a high cost and go od effect solution. by different application and system requirement to select suitable reset ic. the reset circuit can improve all power variation . mcu vdd vss vcc gnd r s t r1 47k ohm r3 2k ohm r2 10k ohm q1 e c b mcu vdd vss vcc gnd r s t reset ic vdd vss rst bypass capacitor 0.1uf
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 50 version 1. 5 4 4 4 system clock 4.1 overview the micro - controller is a dual clock system including high - speed and low - speed cloc ks. the high - speed clock includes internal high - speed oscillator and external oscillators selected by high_clk code option. the low - speed clock is from internal low - speed oscillator controlled by clkmd bit of oscm register. both high - speed clock and lo w - speed clock can be system clock source through a divider to decide the system clock rate. ? high - speed oscillator internal high - speed oscillator is 16mhz rc type called ihrc . external high - speed oscillator includes crystal/ ceramic (4mhz, 12mhz, 32khz) and rc type. ? low - speed oscillator internal low - speed oscillator is 16khz @3v, 32khz @5v rc type called ilrc . ? system clock block diagram ? hosc: high_clk code option. ? fhosc: external high - speed clock / internal high - spee d rc clock. ? flosc: internal low - speed rc clock (about 16khz@3v, 32khz@5v) . ? fosc: system clock source. ? fcpu: instruction cycle. sonix provides a noise filter controlled by code option. in high noisy situation, the noise filter can isolate noise outside a nd protect system works well. the minimum fcpu of high clock is limited at fhosc/4 when noise filter enable. 4.2 fcpu (instruction cy cle) the system clock rate is instruction cycle called fcpu which is divided from the system clock source and decides the sy stem operating rate. fcpu rate is selected by fcpu code option and the range is fhosc/ 1 ~fhosc/16 under system normal mode. if the system high clock source is external 4mhz crystal, and the fcpu code option is fhosc/4, the fcpu frequency is 4mhz/4 = 1mhz. u nder system slow mode, the fcpu is fixed flosc/4, 16khz/4=4khz @3v, 32khz/4=8khz @5v. the fcpu range is limited by high clock and noise filter code option. if high clock code option is rc, 12m x ? tal , 4m x? tal or 32k x? tal, the fcpu range is fhosc/1~fhosc/1 6. if high clock code option is ihrc_16m or ihrc_rtc, the fcpu range is fhosc/2~fhosc/16. if noise filter code option is disabled, the fcpu range is depended on high clock code option. if noise filter code option is enabled, the fcpu range is fhosc/4~fhosc /16 to reduce noise effect. fhosc. fcpu = fhosc/1 ~ fhosc/16, noise filter disable. fcpu = fhosc/4 ~ fhosc/16, noise filter enable. flosc. fcpu = flosc/4 cpum[1:0] xin xout stphx hosc fcpu code option fosc fosc clkmd fcpu
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 51 version 1. 5 4.3 noise filter the noise filter controlled by noise_filter code option is a low pass filter and supports external oscillator including rc and crystal modes. the purpose is to filter high rate noise coupling on high clock sig nal from external oscillator. in high noisy environment, enable noise_filter code option is the strongly recommend ation to reduce noise effect. 4.4 system high - speed clock the system high - speed clock has internal and external two - type. the external high - s peed clock includes 4mhz, 12mhz, 32khz crystal/ ceramic and rc type. these high - speed oscillators are selected by high_clk code option. the internal high - speed clock supports real time clock (rtc) function. under ihrc_rtc mode, the internal high - speed c lock and external 32khz oscillator active. the internal high - speed clock is the system clock source, and the external 32khz oscillator is the rtc clock source to supply a accurately real time clock rate. 4.4.1 high_clk code option for difference clock function s, sonix provides multi - type system high clock options controlled by high_clk code option. the high_clk code option defines the system oscillator types including ihrc_16m, ihrc_rtc, rc, 32k x ? tal, 12m x ? tal and 4m x ? tal. these oscillator options support different bandwidth oscillator. ? ihrc_ 16 m: the system high - speed clock source is internal high - speed 16mhz rc type oscillator. in the mode, xin and xout pins are bi - direction gpio mode, and not to connect any external oscillator device. ? ihrc_rtc: the sys tem high - speed clock source is internal high - speed 16mhz rc type oscillator. the rtc clock source is external low - speed 32768hz crystal. the xin and xout pins are defined to drive external 32768hz crystal and disables gpio function . ? rc: the system high - sp eed clock source is external low cost rc type oscillator. the rc oscillator circuit only connects to xin pin, and the xout pin is bi - direction gpio mode. ? 32k x tal: the system high - speed clock source is external low - speed 32768hz crystal. the option only supports 32768hz crystal and the rtc function is workable. ? 12m x tal: the system high - speed clock source is external high - speed crystal/ceramic. the oscillator bandwidth is 10mhz~16mhz. ? 4m x tal: the system high - speed clock source is external high - speed crystal/resonator. the oscillator bandwidth is 1mhz~10mhz. for power consumption under ihrc_rtc mode, the internal high - speed oscillator and internal low C speed oscillator stops and only external 32khz crystal actives under green mode. the condition is the watchdog timer can ? t be always_on option, or the internal low - speed oscillator actives. 4.4.2 internal high - speed oscillator rc type (ihrc) the internal high - speed oscillator is 16mhz rc type. the accuracy is 2% under commercial condition. when the hig h_clk code option is ihrc_16m or ihrc_rtc , the internal high - speed oscillator is enabled. ? ihrc_16m: the system high - speed clock is internal 16mhz oscillator rc type. xin/xout pins are general purpose i/o pins. ? ihrc_rtc: the system high - speed clock is internal 16mhz oscillator rc type, and the real time clock is external 32768hz crystal. xin/xout pins connect with external 32768hz crystal. 4.4.3 external high - speed oscillator the external high - speed oscillator includes 4mhz, 12mhz, 32khz and rc type. the 4mhz, 12mhz and 32khz oscillators support crystal and ceramic types connected to xin/xout pins with 20pf capacitors to ground. the rc type is a low cost rc circuit only connected to xin pin. the capacitance is not below 100pf , and use the resistance to dec ide the frequency.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 52 version 1. 5 4.4.4 external oscillator application circuit crystal/ceramic rc type ? note: connect the crystal/ceramic and c as near as possible to the xin/xout/vss pins of micro - controller . connect the r and c as near as possible to the vdd pin of micro - controller. mcu vcc gnd c 20pf xin x o u t vdd v s s c 20pf crystal r mcu vcc gnd xin x o u t v d d vss c
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 53 version 1. 5 4.5 system low - speed clock the system low clock source is the internal low - speed oscillator built in the micro - controller. t he low - speed oscillator uses rc type oscillator circu it. the frequency is affected by the voltage and temperature of the system. in common condition, the frequency of the rc oscillator is about 16khz at 3v and 32khz at 5v . the relation between the rc frequency and voltage is as the following figure . the internal low rc supports watchdog clock source and system slow mode controlled by clkmd bit of oscm register. ? flosc = internal low rc oscillator (about 16khz @3v, 32khz @5v) . ? slow mode fcpu = flosc / 4 there are two conditions to stop internal low rc. one is power down mode, and the other is green mode of 32k mode and watchdog disable. if system is in 32k mode and watchdog disable, only 32k oscillator actives and system is under low power consumption. ? example: stop internal low - speed oscillator by power down mode. b0bset fcpum0 ; to stop external high - speed oscillator and internal low - speed ; oscillator called power down mode (sleep mode). ? note: the internal low - speed clock can t be turned off individually . it is controlled by cpum0, cpum 1 (32k, watchdog disable) bits of oscm register. internal low rc frequency 7.52 10.64 14.72 16.00 17.24 18.88 22.24 25.96 29.20 32.52 35.40 38.08 40.80 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 2.1 2.5 3 3.1 3.3 3.5 4 4.5 5 5.5 6 6.5 7 vdd (v) freq. (khz) ilrc
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 54 version 1. 5 4.6 oscm register the oscm register is a n oscillator control register. it control s oscillator status, system mode. 0 ca h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 oscm 0 0 0 cpum1 cpum0 clkmd stph x 0 read/write - - - r/w r/w r/w r/w - after reset - - - 0 0 0 0 - bit 1 stphx: e xternal high - speed oscillator control bit. 0 = external high - speed oscillator f ree run . 1 = external high - speed oscillator f ree run s top. i nternal low - speed rc oscillato r is still running. bit 2 clkmd: system high/low clock mode control bit. 0 = n ormal (dual) mode . system clock is high clock. 1 = s low mode. system clock is internal low clock. bit[4:3] cpum [1:0] : cpu operating mode control bit s . 00 = normal . 01 = sle ep (power down) mode . 10 = green mode . 11 = reserved. stphx bit controls internal high speed rc type oscillator and external oscillator operations. when stphx=0 , the external oscillator or internal high speed rc type oscillator active. when stphx=1 , the external oscillator or internal high speed rc type oscillator are disabled. the stphx function is depend on different high clock options to do different controls. ? ihrc_ 16 m: stphx=1 disables internal high speed rc type oscillator. ? ihrc_rtc: stph x=1 disables internal high speed rc type oscillator and external 32768hz crystal. ? rc, 4m, 12m, 32k: stphx=1 disables external oscillator. 4.7 system clock measurement under design period, the users can measure system clock speed by software instruction cycle (fcpu). this way is useful in rc mode. ? example: fcpu instruction cycle of external oscillator . b0bset p0m.0 ; set p0.0 to be output mode for outputting fcpu toggle signal. @@: b0bset p0.0 ; o utput fcpu toggle signal in low - speed cloc k mode. b0bclr p0.0 ; measure the fcpu frequency by oscilloscope . jmp @b ? note: do not measure the rc frequency directly from xin; the probe impendence will affect the rc frequency.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 55 version 1. 5 4.8 system clock timing parameter symbol description typical hardware configuration time tcfg 2048*f ilrc 64ms @ f ilrc = 32khz 128ms @ f ilrc = 16khz oscillator start up time tost the start - up time is depended on oscillator?s material, factory and architecture. normally, the low - speed oscillator?s start - up time is lower than high - speed oscillator. the rc type oscillator?s start - up time is faster than crystal type oscillator. - oscillator warm - up time tosp oscillator warm - up time of reset condition . 2048*f hosc (power on reset, lvd reset, watchdog reset, external reset pin active.) 64ms @ f hosc = 32khz 512us @ f hosc = 4mhz 128 us @ f hosc = 16 mhz oscillator warm - up time of power down mode wake - up condition . 2048*f hosc crystal/resonator type oscillator, e.g. 32768hz crystal, 4mhz crystal, 16mhz crystal 32 *f hos c rc type oscillator , e.g. external rc type oscillator, internal high - speed rc type oscillator. x ? tal: 64ms @ f hosc = 32khz 512us @ f hosc = 4mhz 128 us @ f hosc = 16 mhz rc: 8u s @ f hosc = 4m hz 2u s @ f hosc = 16m hz ? power on reset timing ? external reset pi n reset timing v d d p o w e r o n r e s e t f l a g o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t c f g t o s t t o s p v p e x t e r n a l r e s e t p i n o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t c f g t o s t t o s p r e s e t p i n f a l l i n g e d g e t r i g g e r s y s t e m r e s e t . r e s e t p i n r e t u r n s t o h i g h s t a t u s . s y s t e m i s u n d e r r e s e t s t a t u s . e x t e r n a l r e s e t f l a g
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 56 version 1. 5 ? watchdog reset timing ? power down mode wake - up timing ? green mode wake - up timing w a t c h d o g r e s e t f l a g o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t c f g t o s t t o s p w a t c h d o g t i m e r o v e r f l o w . w a k e - u p p i n r i s i n g e d g e o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) t o s p t o s t w a k e - u p p i n f a l l i n g e d g e s y s t e m i n s e r t s i n t o p o w e r d o w n m o d e . e d g e t r i g g e r s y s t e m w a k e - u p . w a k e - u p p i n r i s i n g e d g e o s c i l l a t o r f c p u ( i n s t r u c t i o n c y c l e ) w a k e - u p p i n f a l l i n g e d g e s y s t e m i n s e r t s i n t o g r e e n m o d e . e d g e t r i g g e r s y s t e m w a k e - u p . 0 x 0 0 0 x f f 0 x f e 0 x 0 1 0 x 0 2 . . . 0 x f d . . . . . . . . . . . . . . . t i m e r t i m e r o v e r f l o w .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 57 version 1. 5 ? oscillator start - up time the start - up time is depended on oscillator?s material, factory and architecture. normally, the low - speed oscillator?s st art - up time is lower than high - speed oscillator. the rc type oscillator?s start - up time is faster than crystal type oscillator. l o w s p e e d c r y s t a l ( 3 2 k , 4 5 5 k ) t o s t c r y s t a l t o s t r c o s c i l l a t o r t o s t c e r a m i c / r e s o n a t o r t o s t
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 58 version 1. 5 5 5 5 system operation mode 5.1 overview the chip builds in four operating mode for difference clock rat e and power saving reason. these modes control oscillators, op - code operation and analog peripheral devices ? operation. ? normal mode: system high - speed operating mode. ? slow mode: system low - speed operating mode. ? p ower down mode : system power saving mode (sleep mode). ? green mode : system ideal mode. operating mode control block operating mode clock control table operating m ode normal mode slow mode green mode power down mode ehosc running by stphx by stphx stop ihrc runn ing by stphx by stphx stop ilrc running running running stop ehosc with rtc running by stphx running stop ihrc with rtc running by stphx stop stop ilrc with rtc running running stop stop cpu instruction executing executing stop stop t0 timer by t0enb by t0enb by t0enb inactive tc 0 timer by tc 0 enb by tc 0 enb by tc 0 enb ( pwm/buzzer active ) inactive t 1 timer by t 1 enb by t 1 enb by t 1 enb inactive pwm1, pwm2 by pwnen by pwnen by pwnen inactive w atchdog timer by watch_dog code option by watch_dog code opt ion by watch_dog code option by watch_dog code option internal interrupt all active all active t0 , t1 all inactive external interrupt all active all active all active all inactive wakeup source - - p0, p1, t0 , t1, reset p0, p1, reset ? ehosc: externa l high - speed oscillator (xin/xout). ? i h rc: internal high - speed oscillator rc type. ? ilrc: internal low - speed oscillator rc type. p o w e r d o w n m o d e s l o w m o d e c l k m d = 1 c l k m d = 0 c p u m 1 , c p u m 0 = 0 1 . w a k e - u p c o n d i t i o n : p 0 , p 1 i n p u t s t a t u s i s l e v e l c h a n g i n g . t 0 , t 1 t i m e r c o u n t e r i s o v e r f l o w . c p u m 1 , c p u m 0 = 1 0 . n o r m a l m o d e g r e e n m o d e w a k e - u p c o n d i t i o n : p 0 , p 1 i n p u t s t a t u s i s l e v e l c h a n g i n g . t 0 , t 1 t i m e r c o u n t e r i s o v e r f l o w . w a k e - u p c o n d i t i o n : p 0 , p 1 i n p u t s t a t u s i s l e v e l c h a n g i n g . r e s e t c o n t r o l b l o c k o n e o f r e s e t t r i g g e r s o u r c e s a c t i v e s . o n e o f r e s e t t r i g g e r s o u r c e s a c t i v e s . o n e o f r e s e t t r i g g e r s o u r c e s a c t i v e s .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 59 version 1. 5 5.2 normal mode the normal mode is system high clock operating mode. the system clock source is from high speed oscillator. the program is executed. after power on and any reset trigger released, the system inserts into normal mode to execute program. when the system is wake - up from power down mode, the system also inserts into normal mode. in normal mode, the high speed oscillato r actives, and the power consumption is largest of all operating modes. ? the program is executed, and full functions are controllable . ? the system rate is high speed. ? the high speed oscillator and internal low speed rc type oscillator active. ? normal mod e can be switched to other operating modes through oscm register. ? power down mode is wake - up to normal mode. ? slow mode is switched to normal mode. ? green mode from normal mode is wake - up to normal mode. 5.3 slow mode the slow mode is system low clock opera ting mode. the system clock source is from internal low speed rc type oscillator. the slow mode is controlled by clkmd bit of oscm register. when clkmd=0, the system is in normal mode. when clkmd=1, the system inserts into slow mode. the high speed oscilla tor won?t be disabled automatically after switching to slow mode, and must be disabled by spthx bit to reduce power consumption. in slow mode, the system rate is fixed flosc/4 (flosc is internal low speed rc type oscillator frequency). ? the program is exe cuted, and full functions are controllable . ? the system rate is low speed (flosc/4). ? the internal low speed rc type oscillator actives, and the high speed oscillator is controlled by stphx=1. in slow mode, to stop high speed oscillator is strongly recomme ndation . ? slow mode can be switched to other operating modes through oscm register. ? power down mode from slow mode is wake - up to normal mode. ? normal mode is switched to slow mode. ? green mode from slow mode is wake - up to slow mode. 5.4 power down mdoe the power down mode is the system ideal status. no program execution and oscillator operation. whole chip is under low power consumption status under 1ua. the power down mode is waked up by p0, p1 hardware level change trigger. p1 wake - up function is controlle d by p1w register. any operating modes into power down mode, the system is waked up to normal mode. inserting power down mode is controlled by cpum0 bit of oscm register. w h en cpum0=1, the system inserts into power down mode. after system wake - up from powe r down mode, the cpum0 bit is disabled (zero status) automatically. ? the program stops executing, and full functions are disabled. ? all oscillators including external high speed oscillator, internal high speed oscillator and internal low speed oscillator stop. ? the power consumption is under 1ua. ? the system inserts into normal mode after wake - up from power down mode. ? t h e power down mode wake - up source is p0 and p1 level change trigger. ? note: if the system is in normal mode, to set stphx=1 to disable t he high clock oscillator. the system is under no system clock condition. this condition makes the system stay as power down mode, and can be wake - up by p0, p1 level change trigger.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 60 version 1. 5 5.5 green mode the green mode is another system ideal status not like po wer down mode. in power down mode, all functions and hardware devices are disabled. but in green mode, the system clock source keeps running, so the power consumption of green mode is larger than power down mode. in green mode, the program isn?t executed, but the timer with wake - up function actives as enabled, and the timer clock source is the non - stop system clock. the green mode has 2 wake - up sources. one is the p0, p1 level change trigger wake - up. the other one is internal timer with wake - up function occ urring overflow. that ? s mean users can setup one fix period to timer, and the system is waked up until the time out. inserting green mode is controlled by cpum1 bit of oscm register. w h en cpum1=1, the system inserts into green mode. after system wake - up fr om green mode, the cpum1 bit is disabled (zero status) automatically. ? the program stops executing, and full functions are disabled. ? only the timer with wake - up function actives. ? the oscillator to be the system clock source keeps running, and the other oscillators operation is depend on system operation mode configuration. ? if inserting green mode from normal mode, the system insets to normal mode after wake - up. ? if inserting green mode from slow mode, the system insets to slow mode after wake - up. ? the g reen mode wake - up sources are p0, p1 level change trigger and unique time overflow. ? pwm and buzzer output functions active in green mode , but the timer can ? t wake - up the system as overflow. ? note: sonix provides greenmode macro to control green mode o peration. it is necessary to use greenmode macro to control system inserting green mode. the macro includes three instructions. please take care the macro length as using branch type instructions , e.g. bts0, bts1, b0bts0, b0bts1, ins, incms, decs, decms , cmprs, jmp, or the routine would be error.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 61 version 1. 5 5.6 operating mode contr ol macro sonix provides operating mode control macros to switch system operating mode easily. macro length description sleepmode 1 - word the system insets into sleep mode (power down mode). greenmode 3 - word the system inserts into green mode. slowmode 2 - word the system inserts into slow mode and stops high speed oscillator. slow2normal 5 - word the system returns to normal mode from slow mode. the macro includes operating mode swit ch, enable high speed oscillator, high speed oscillator warm - up delay time. ? example: switch normal/slow mode to power down (sleep) mode. sleepmode ; declare ? example: switch normal mode to slow mode. slowmode ; decla re ? example: switch slow mode to normal mode (t he external high - speed oscillator stops ). slow2normal ; declare slow2normal macro directly. ? example: switch normal/slow mode to green mode. greenmode ; declare ? example: switch normal/slow mode to green mode and enable t0 wake - up function . ; set t0 timer wakeup function . b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0enb ; to disable t0 timer mov a,#20h ; b0mov t0m, a ; to set t0 clock = fcpu / 64 mov a,#74h b0mov t0c,a ; to set t0c initial value = 74h (to set t0 interval = 10 ms) b0bclr ft0ien ; to disable t0 interrupt service b0bclr ft0irq ; to clear t0 interrupt request b0bset ft0enb ; to enable t0 timer ; go into green mode greenmode ; declare ? example: switch normal/slow mode to green mode and enable t0 wake - up function with rtc . clr t0c ; clear t0 counter. b0bset ft0 tb ; enable t0 rtc function. b0bset f t0enb ; to enable t0 timer . ; go into green mode greenmode ; declare
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 62 version 1. 5 5.7 wakeup 5.7.1 overview under power down mode (sleep mode) or green mode , program doesn ? t execute. the wakeup trigger can wake the system up to norma l mode or slow mode. the wakeup trigger sources are external trigger (p0/p1 level change) and internal trigger (t0/t1 timer overflow). ? power down mode is waked up to normal mode. the wakeup trigger is only external trigger (p0/p1 level change) ? green mode is waked up to last mode (normal mode or slow mode). the wakeup triggers are external trigger (p0/p1 level change) and internal trigger (t0/t1 timer overflow). 5.7.2 wakeup time when the system is in power down mode (sleep mode), the high clock oscillator stop s. when waked up from power down mode, mcu waits for 2048 external high - speed oscillator clocks and 32 internal high - speed oscillator clocks as the wakeup time to stable the oscillator circuit. after the wakeup time, the system goes into the normal mode. ? note : wakeup from green mode is no wakeup time because the clock doesnt stop in green mode. the value of the external high clock oscillator wakeup time is as the following. the wakeup time = 1/fosc * 2048 (sec) + high clock start - up time example: in power down mode (sleep mode), the system is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/fosc * 2048 = 0.512 ms (fosc = 4 mhz ) the total wakeup time = 0.512 ms + oscillato r start - up time the value of the internal high clock oscillator rc type wakeup time is as the following. the wakeup time = 1/fosc * 32 (sec) + high clock start - up time example: in power down mode (sleep mode), the system is waked up. after the wakeup time, the system goes into normal mode. the wakeup time is as the following. the wakeup time = 1/fosc * 32 = 2 u s (fhosc = 16 mhz ) ? note : the high clock start - up time is depended on the vdd and oscillator type of high clock.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 63 version 1. 5 5.7.3 p1w wakeup control r egister under power down mode (sleep mode) and green mode, the i/o ports with wakeup function are able to wake the system up to normal mode. the wake - up trigger edge is level changing. when wake - up pin occurs rising edge or falling edge, the system is wake d up by the trigger edge. the port 0 and port 1 have wakeup function. port 0 wakeup function always enables, but the port 1 is controlled by the p1w register. 0c0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p1w p17w p16w p15w p14w p13w p12w p11w p1 0w read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit[7:0] p10w~p17w: port 1 wakeup function control bits. 0 = disable p1n wakeup function. 1 = enable p1n wakeup function.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 64 version 1. 5 6 6 6 interrupt 6.1 overview th is mcu provides 10 interrupt sources, includin g 7 internal interrupt ( t0/t1/ tc 0/cm0/cm1/cm2/adc ) and 3 external interrupt (int0 /int1/int2 ). the external interrupt can wakeup the chip while the system is switched from power down mode to high - speed normal mode , and interrupt request is latched until ret urn to normal mode . once interrupt service is executed, the gie bit in stkp register will clear to 0 for stopping other interrupt request. on the contrast, when interrupt service exits, the gie bit will set to 1 to accept the next interrupts? request. most of the interrupt request signals are stored in intrq register , but comparator interrupt request flags are stored in cmnm registers. ? note : the gie bit must enable during all interrupt operation. i n t e n i n t e r r u p t e n a b l e r e g i s t e r i n t e r r u p t e n a b l e g a t i n g i n t r q 7 - b i t & c m n m 3 - b i t l a t c h s p 0 0 i r q p 0 1 i r q p 0 2 i r q i n t e r r u p t v e c t o r a d d r e s s ( 0 0 0 8 h ) g l o b a l i n t e r r u p t r e q u e s t s i g n a l i n t 0 t r i g g e r t 0 t i m e o u t t c 0 t i m e o u t a d c c o n v e r t i n g e n d t 0 i r q i n t 1 t r i g g e r i n t 2 t r i g g e r c o m p a r a t o r 0 t r i g g e r c o m p a r a t o r 1 t r i g g e r c o m p a r a t o r 2 t r i g g e r t c 0 i r q a d c i r q c m 0 i r q c m 1 i r q c m 2 i r q t 1 t i m e o u t t 1 i r q
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 65 version 1. 5 6.2 inten interrupt enable register inten is the interrupt request control register including four internal interrupts, three external interrupts enable control bits. one of the register to be set 1 is to enable the interrupt request function. once of the interrupt occur, the stack is incremented and program jump to org 8 to execute interrupt service routines. the program exits the interrupt service routine when the returning interrupt service routine instruction (reti) is executed. 0 c9 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 inten adcien t 1 ien tc0ien t0ien - p0 2i en p01ien p00ien read/write r/w r/w r/w r/w - r/w r/w r/w after reset 0 0 0 0 - 0 0 0 bit 0 p00ien: external p0.0 interrupt (int0) control bit. 0 = d isable int0 interrupt function . 1 = en able int0 i nterrupt function . bit 1 p0 1 ien: external p0. 1 interrupt (int1) control bit. 0 = d isable int1 interrupt function . 1 = en able int1 interrupt function . bit 2 p0 2 ien: external p0. 2 interrupt (int2) control bit. 0 = d isable int2 interrupt function . 1 = en a ble int2 interrupt function . bit 4 t0 ien: t0 timer interrupt control bit. 0 = d isable t0 interrupt function . 1 = en able t0 interrupt function . bit 5 t c 0ien: tc0 t imer interrupt control bit. 0 = d isable tc0 interrupt function . 1 = en able tc0 interrupt f unction . bit 6 t 1 ien: t1 t imer interrupt control bit. 0 = d isable t1 interrupt function . 1 = en able t1 interrupt function . bit 7 adc ien: adc interrupt control bit. 0 = d isable adc interrupt function . 1 = en able adc interrupt function . cm0ien (cm p 0m s bit 6): comparator 0 interrupt control bit. 0 = d isable comparator 0 interrupt function . 1 = en able comparator 0 interrupt function . cm1ien (cm p 1m s bit 6): comparator 1 interrupt control bit. 0 = d isable comparator 1 interrupt function . 1 = en able compa rator 1 interrupt function . cm2ien (cm p 2 m s bit 6): comparator 2 interrupt control bit. 0 = d isable comparator 2 interrupt function . 1 = en able comparator 2 interrupt function .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 66 version 1. 5 6.3 intrq interrupt requ est register intrq is the interrupt request flag regis ter. the register includes all interrupt request indication flags. each one of the interrupt request s occurs, the bit of the intrq register would be set 1. the intrq value needs to be clear by programming after detecting the flag. in the interrupt vector of program, users know the any interrupt requests occurring by the register and do the routine corresponding of the interrupt request. 0 c8 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 intrq adcirq t 1 irq tc0irq t0irq - p0 2 irq p01irq p00irq read/wri te r/w r/w r/w r/w - r/w r/w r/w after reset 0 0 0 0 - 0 0 0 bit 0 p00i rq : external p0.0 interrupt (int0) request flag . 0 = non e int0 interrupt request . 1 = int0 interrupt request . bit 1 p0 1 i rq : external p0. 1 interrupt (int1) request flag . 0 = non e i nt1 interrupt request . 1 = int1 interrupt request . bit 2 p0 2 i rq : external p0. 2 interrupt (int2) request flag . 0 = non e int2 interrupt request . 1 = int2 interrupt request . bit 4 t0 i rq : t0 timer interrupt request flag . 0 = non e t0 interrupt request . 1 = t0 interrupt request . bit 5 t c 0i rq : tc0 t imer interrupt request flag. 0 = non e tc0 interrupt request . 1 = tc0 interrupt request . bit 6 t 1 i rq : t1 t imer interrupt request flag. 0 = non e t1 interrupt request . 1 = t1 interrupt request . bit 7 adc i rq : adc interrupt request flag. 0 = non e adc interrupt request . 1 = adc interrupt request . cm0i rq (cm p 0m s bit 5 ): comparator 0 interrupt request flag. 0 = non e comparator 0 interrupt request . 1 = comparator 0 interrupt request . cm 1 i rq (cm p 1 m s bit 5 ): comparator 1 interrupt request flag. 0 = non e comparator 1 interrupt request . 1 = comparator 1 interrupt request . cm 2 i rq (cm p 2 m s bit 5 ): comparator 2 interrupt request flag. 0 = non e comparator 2 interrupt request . 1 = comparator 2 interrupt request .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 67 version 1. 5 6.4 gie global interrupt operation gie is the global interrupt control bit. all interrupts start work after the gie = 1 it is necessary for interrupt service request. one of the interrupt requests occurs, and the program counter (pc) points to the interrupt vector (org 8 ) and the stack add 1 level. 0dfh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 stkp gie - - - - stkpb2 stkpb1 stkpb0 read/write r/w - - - - r/w r/w r/w after reset 0 - - - - 1 1 1 bit 7 gie: global interrupt control bit. 0 = disable global int errupt. 1 = enable global interrupt. example: set global interrupt control bit (gie). b0bset fgie ; enable gie ? note: the gie bit must enable during all interrupt operation.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 68 version 1 . 5 6.5 push, pop routine when any interrupt occurs, system will jump to or g 8 and execute interrupt service routine. it is necessary to save acc, pflag data. the chip includes push , pop for in/out interrupt service routine. the two instructions save and load acc , pflag data into buffers and avoid main routine error after int errupt service routine finishing. ? note : push , pop instructions save and load acc/pflag without ( nt0, npd). push/pop buffer is an unique buffer and only one level . ? example: store acc and paflg data by push, pop instructions when interrupt servic e routine executed. org 0 jmp start org 8 jmp int_service org 10h start: push ; save acc and pflag to buffers. pop ; l oad acc and pflag from buffers. reti ; exit inter rupt service vector
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 69 version 1 . 5 6.6 external interrupt o peration (int0~int2) sonix provides 3 sets external interrupt source s in the micro - controller. int0, int1 and int2 are external interrupt trigger sources and build in edge trigger configuratio n function. when the external edge trigger occurs, the external interrupt request flag will be set to 1 when the external interrupt control bit enabled. if the external interrupt control bit is disabled, the external interrupt request flag won ? t active w hen external edge trigger occurrence. when external interrupt control bit is enabled and external interrupt edge trigger is occurring, the program counter will jump to the interrupt vector (org 8) and execute interrupt service routine. the external interr upt builds in wake - up latch function. that means when the system is triggered wake - up from power down mode , the wake - up source is external interrupt source (p0.0, p0.1 or p0.2), and the trigger edge direction matches interrupt edge configuration, the trigg er edge will be latched, and the system executes interrupt service routine fist after wake - up. 0 b fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pedge - - p02g1 p02g0 p01g1 p01g0 p00g1 p00g0 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 bit[ 5 : 4 ] p0 2 g[1:0]: int2 edge trigger select bits. 00 = reserved, 01 = ris ing edge, 10 = falling edge, 11 = rising/falling bi - direction. bit[ 3 : 2 ] p0 1 g[1:0]: int1 edge trigger select bits. 00 = reserved, 01 = ris ing edge, 10 = falling edge, 11 = rising/falling bi - direction. bit[ 1 : 0 ] p0 0 g[1:0]: int0 edge trigger select bits. 00 = reserved, 01 = ris ing edge, 10 = falling edge, 11 = rising/falling bi - direction. example: setup int0 interrupt request and bi - direction edge trigger. mov a, #03h b 0mov pedge, a ; set int0 interrupt trigger as bi - direction edge. b0bset fp00ien ; e nable int0 interrupt service b0bclr f p00 irq ; c lear int0 interrupt request flag b0bset fgie ; enable gie example: int0 interrupt service routine. org 8 ; inte rrupt vector jmp int_service int_service: ; push routine to save acc and pflag to buffers. b0bts1 fp00irq ; check p00irq jmp exit_int ; p00irq = 0, exit interrupt vector b0bclr fp00irq ; reset p00irq exit_int: ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 70 version 1 . 5 6.7 t0 interrupt operati on when the t0c counter occurs overflow, the t0irq will be set to 1 however the t0ien is enable or disable. if the t0i en = 1, the trigger event will make the t0irq to be 1 and the system enter interrupt vector. if the t0ien = 0, the trigger event will make the t0irq to be 1 but the system will not enter interrupt vector. users need to care for the operation under mult i - interrupt situation. ? example: t0 interrupt request setup. fcpu = 4mhz / 4. b0bclr ft 0 ien ; d isable t 0 interrupt service b0bclr ft 0 enb ; d isable t 0 timer mov a, #20h ; b0mov t 0 m, a ; s et t 0 clock = f cpu / 64 mov a, # 6 4h ; s et t 0 c initial value = 6 4h b0mov t 0 c, a ; s et t 0 interval = 10 ms b0bset ft 0 ien ; e nable t 0 interrupt service b0bclr ft 0 irq ; c lear t 0 interrupt request flag b0bset ft 0 enb ; e nable t 0 timer b0bset fgie ; enable gie ? example: t0 interrupt service routine . org 8 ; interrupt vector jmp int_service int_service: b0bts1 ft0irq ; check t0irq jmp exit_int ; t0irq = 0, exit interrupt vector b0bclr ft0irq ; reset t0irq mov a, #6 4h b0mov t0c, a ; reset t0c. ; t0 interrupt service routine
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 71 version 1 . 5 6.8 tc0 interrupt operat ion when the tc0c counter overflows, the tc0i rq will be set to 1 no matter the tc0ien is enable or disable. if the tc0ien and the trigger event tc0irq is set to be 1. as the result, the system will execute the interrupt vector. if the tc0ien = 0, the trigger event tc0irq is still set to be 1. moreover, the system won?t execute interrupt vector even when the tc0ien is set to be 1. users need to be cautious with the operation under multi - interrupt situation. ? example: tc0 interrupt request setup. fcpu = 16mhz / 16. b0bclr ftc0ien ; disable t c0 interrupt service b0bclr ftc0enb ; disable tc0 timer mov a, #20h ; b0mov tc0m, a ; set tc0 clock = fcpu / 64 mov a, # 6 4h ; set tc0c initial value = 6 4h b0mov tc0c, a ; set tc0 interval = 10 ms b0bset ftc0ien ; enable tc0 interrupt serv ice b0bclr ftc0irq ; clear tc0 interrupt request flag b0bset ftc0enb ; enable tc0 timer b0bset fgie ; enable gie ? example: tc0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 ftc0irq ; check tc0irq jmp exit_int ; tc0irq = 0, exit interrupt vector b0bclr ftc0irq ; reset tc0irq mov a, # 6 4h b0mov tc0c, a ; reset tc0c. ; tc0 interrupt service routine
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 72 version 1 . 5 6.9 t1 interrupt operati on when the t 1 c (t1ch, t1cl) counter occurs overflow, the t 1 irq will be set to 1 however the t 1 ien is enable or disable. if the t 1 ie n = 1, th e trigger event will make the t 1 irq to be 1 and the system e nter interrupt vector. if the t 1 ien = 0, th e trigger event will make the t 1 irq to be 1 but the system will not enter interrupt vector. users need to care for the operation under multi - interrupt situation. ? example: t1 interrupt request setup. b0bclr ft1ien ; d isable t1 interrupt service b0bclr ft1enb ; d isable t1 timer mov a, #20h ; b0mov t1m, a ; s et t1 clock = f cpu / 32. clr t1ch clr t1cl b0bset ft1ien ; e nable t1 interrupt service b0bclr ft1irq ; c lear t1 interrupt request flag b0bset ft1enb ; e nable t1 timer b0bset fgie ; enable gie example: t1 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: push ; push routine to save acc and pflag to buffers. b0bts1 ft1irq ; check t1irq jmp exit_int ; t1irq = 0, exit interrupt vector b0bclr ft1irq ; reset t1irq b0mov a, t1c l b0mov t1c l buf, a b0mov a, t1c h b0mov t1c h buf, a ; save pulse w idth. clr t1ch clr t1cl exit_int: pop ; pop routine to load acc and pflag from buffers. reti ; exit interrupt vector
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 73 version 1 . 5 6.10 adc interrupt operat ion when the adc converting successfully, the adci rq will be set to 1 no matter the adcien is enable or disable. if the adcien and the trigger event adcirq is set to be 1 . as the result, the system will execute the interrupt vector. if the adcien = 0, the trigger event adcirq is still set to be 1 . moreover, the system won ? t execute interrupt vector even when the adcien is set to be 1 . users need to be cautious with the operation under multi - interrupt situation. ? example: adc interrupt request setup. b0bclr f adc ien ; d isable adc interrupt servic e mov a, # 10110000b ; b0mov adm , a ; enable p4.0 adc input and adc function. mov a, # 00000000b ; s et adc converting rate = fcpu/16 b0mov adr , a b0bset f adc ien ; e nable adc interrupt service b0bclr f adc irq ; c lear adc interrupt reques t flag b0bset fgie ; enable gie b0bset f ads ; start adc transformation ? example: adc interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: b0bts1 fadcirq ; check adcirq jmp exit_int ; adcirq = 0, exit interrupt vector b0bclr fadcirq ; reset adcirq ; adc interrupt service routine
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 74 version 1 . 5 6.11 comparator interrupt operation (cmp0~cmp2 ) sonix provides 3 sets comparator with interrupt function in the micro - controller. the comparator interrupt trigger edge direction is controlled by comparator register. cm0g[1:0] of cm p 0m is contr ol comparator 0 interrupt trigger edge direction. cm1g[1:0] of cm p 1m is control comparator 1 interrupt trigger edge direction. cm2g[1:0] of cm p 2m is control comparator 2 interrupt trigger edge direction. when the comparator output status transition occurs, t he comparator interrupt request flag will be set to 1 no matter the comparator interrupt control bit status. the comparator interrupt flag doesn? t active only when comparator control bit is disabled. when comparator interrupt control bit is enabled and c omparator interrupt edge trigger is occurring, the program counter will jump to the interrupt vector (org 8) and execute interrupt service routine. 09ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm p 0m cm0en cm0ien cm0irq cm0oen cm0ref cm0out cm0g1 cm0g0 read/write r/w r/w r/w r/w r/w r r/w r/w after reset 0 0 0 0 0 0 0 0 bit 6 cm0ien: comparator 0 interrupt function control bit. 0 = disable. 1 = enable. bit 5 cm0irq: comparator 0 interrupt request bit. 0 = non comparator interrupt request. 1 = announce comparator interrupt request. bit [1:0] cm0g[1:0]: comparator interrupt trigger direction control bit. 00 = reserved. 01 = rising edge trigger. cm0p > cm0n or comparator internal reference voltage. 10 = falling edge trigger. cm0p < cm0n or comparator internal reference voltage. 11 = both rising and falling edge trigger (level change trigger). 09dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm p 1m cm1en cm1ien cm1irq cm1oen cm1ref cm1out cm1g1 cm1g0 read/write r/w r/w r/w r/w r/w r r/ w r/w after reset 0 0 0 0 0 0 0 0 bit 6 cm1ien: comparator 1 interrupt function control bit. 0 = disable. 1 = enable. bit 5 cm1irq: comparator 1 interrupt request bit. 0 = non comparator interrupt request. 1 = announce comparator interrupt request. bit [1:0] cm1g[1:0]: comparator interrupt trigger direction control bit. 00 = reserved. 01 = rising edge trigger. cm1p > cm1n or comparator internal reference voltage. 10 = falling edge trigger. cm1p < cm1n or comparator internal reference voltage. 1 1 = both rising and falling edge trigger (level change trigger). 09eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cm p 2m cm2en cm2ien cm2irq cm2oen cm2ref cm2out cm2g1 cm2g0 read/write r/w r/w r/w r/w r/w r r/w r/w after reset 0 0 0 0 0 0 0 0 bit 6 cm2ien: comparator 2 interrupt function control bit. 0 = disable. 1 = enable. bit 5 cm2irq: comparator 2 interrupt request bit. 0 = non comparator interrupt request. 1 = announce comparator interrupt request. bit [1:0] cm2g[1:0]: comparator interrupt trigger direction control bit. 00 = reserved. 01 = rising edge trigger. cm2p > cm2n or comparator internal reference voltage. 10 = falling edge trigger. cm2p < cm2n or comparator internal reference voltage. 11 = both rising and falling edge trigger ( level change trigger).
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 75 version 1 . 5 example: setup comparator 0 interrupt request and bi - direction edge trigger. mov a, #03h b0mov cm p 0m, a ; set comparator 0 interrupt trigger as bi - direction edge. b0bset f cm0 ien ; e nable comparator 0 interrupt service b 0bclr f cm0 irq ; c lear comparator 0 interrupt request flag b0bset f cm0 en ; e nable comparator 0. b0bset fgie ; enable gie example: comparator 0 interrupt service routine. org 8 ; interrupt vector jmp int_service int_service: ; push rout ine to save acc and pflag to buffers. b0bts1 fcm0irq ; check cm0irq jmp exit_int ; cm0irq = 0, exit interrupt vector b0bclr fcm0irq ; reset cm0irq exit_int: ; pop routine to load acc an d pflag from buffers. reti ; exit interrupt vector
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd pa ge 76 version 1. 5 6.12 multi - interrupt operation under certain condition, the software designer uses more than one interrupt requests. processing multi - interrupt request requires setting the priority of the interrupt req uests. the irq flags of interrupts are controlled by the interrupt event. nevertheless, the irq flag 1 doesn ? t mean the system will execute the interrupt vector. in addition, which means the irq flags can be set 1 by the events without enable the inter rupt. once the event occurs, the irq will be logic 1 . the irq and its trigger event relationship is as the below table. interrupt name trigger event description p00irq p0.0 trigger controlled by pedge p01irq p0.1 trigger controlled by pedge p02irq p0 .2 trigger controlled by pedge t0irq t0c overflow t1irq t1ch, t1cl overflow tc0irq tc0c overflow adcirq adc converting end. cm0irq comparator 0 output level transition. cm1irq comparator 1 output level transition. cm2irq comparator 2 output level transition. for multi - interrupt conditions, two things need to be taking care of . one is to set the priority for these interrupt requests. two is using ien and irq flags to decide which interrupt to be executed. users have to check interrupt control bit and interrupt request flag in interrupt routine. ? example: check the interrupt request under multi - interrupt operation org 8 ; interrupt vector jmp int_service int_service: intp00c hk: ; check int0 interrupt request b0bts1 fp00ien ; check p00ien jmp intt0chk ; jump check to next interrupt b0bts0 fp00irq ; check p00irq jmp intp00 intt0chk: ; check t0 interrupt request b0bts1 ft0ien ; check t0ien jmp inttc0chk ; jump check to next interrupt b0bts0 ft0irq ; check t0irq jmp intt0 ; j ump to t0 interrupt service routine inttc0chk: ; check tc0 interrupt request b0bts1 ftc0ien ; check tc0ien jmp intadchk ; jump check to next interrupt b0bts0 ftc0irq ; check tc0i rq jmp inttc0 ; j ump to tc0 interrupt service routine intadchk: ; check adc interrupt request b0bts1 fadcien ; check adcien jmp
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 77 version 1. 5 7 7 7 i/o port 7.1 overview the micro - controller builds in 30 pin i/o. most of the i/o pins are mixed with analog pins and special function pins . the i/o shared pin list is as following. i/o pin shared pin shared pin control condition name type name type p0.0 i/o int0 dc p00ien=1 pwm1t dc pw1en=1, pw1gen=1, pw1gs=0 p0.1 i/o int1 dc p01ien=1 pwm 1 dc pw 1 en=1 . p0.2 i/o int2 dc p02ien=1 pwm 1n dc pw 1 en=1, pw1nen=1 p0.3 i rst dc reset_pin code option = reset vpp hv otp programming p0.4 i/o xout ac high_clk code option = ihrc_rtc, 32k, 4m, 12m p0.5 i/o xin ac high_clk code option = ihrc_rtc, rc, 32k, 4m, 12m p1.0 i/o cm 2 n ac cm2en=1 op2n ac op2en=1 p1.1 i/o cm 2 p ac cm2en=1, cm2ref=0 op2p ac op2en=1 p1.2 i/o cm 2 o ac cm2en=1, cm2oen=1 op2o ac op2en=1 p1.3 i/o cm1n ac cm1en=1 op1n ac op1en=1 p1.4 i/o cm1p ac cm1en=1, cm1ref=0 op1p ac op1en=1 p1.5 i/o cm1o ac cm1en=1, cm1oen=1 op1o ac op1en=1 p1. 6 i/o cm 0 n ac cm0en=1 op0n ac op0en=1 p1. 7 i/o cm 0 p ac cm0en=1, cm0ref=0 op0p ac op0en=1 p5.0 i/o cm 0o ac cm0en=1, cm0oen=1 op0o ac op0en=1 p5.1 i/o pwm 21 dc pw2 en=1, pw 2ch1 =1 p5.2 i/o pwm 22 dc pw2 en=1, pw 2ch2 = 1 p5.3 i/o pwm 23 dc pw2 en=1, pw 2ch3 =1 p5.4 i/o bz0/pwm0 dc tc0enb=1, tc0out=1 or pwm0out=1 p5.5 i/o pwm 24 dc pw2 en=1, pw 2ch4 =1 p5.6 i/o pwm 25 dc pw2 en=1, pw 2ch5 =1 p5.7 i/o pwm 26 dc pw2 en=1, pw 2ch6 =1 p4.0 i/o ain0 ac adenb=1, gchs=1, chs[2:1] = 000b avrefh ac adenb=1, avrefh=1 p4 [7:1] i/o ain [7: 1 ] ac adenb=1, gchs=1, chs[2:1] = 001b~111b * dc: digital characteristic. ac: analog characteristic. hv: high voltage characteristic.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 78 version 1. 5 7.2 i/o port mode the port direction is programmed by pnm register. wh en the bit of pnm register is 0 , the pin is input mode. when the bit of pnm register is 1 , the pin is output mode. 0b8h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 0 m - - p 05 m p 04 m - p 02 m p 0 1m p 0 0m read/write - - r/w r/w - r/w r/w r/w after r eset - - 0 0 - 0 0 0 0c1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 1 m p 17 m p 16 m p 15 m p 14 m p 13 m p 12 m p 11 m p 10 m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0 c 4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 4 m p 4 7 m p 46 m p 45 m p 44 m p 43 m p 4 2m p 41 m p 4 0m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0 c 5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 5 m p 57 m p 56 m p 55 m p 54 m p 5 3m p 52 m p 51 m p 50 m read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[7:0] pnm[7:0]: pn mode control bits. (n = 0~5). 0 = pn is input mode. 1 = pn is output mode. ? note : 1. users can program them by bit control instructions (b0bset, b0bclr). 2. p0.3 input only pin, and the p0m.3 is undefined . ? example: i/o mode selecting clr p0m ; set all ports to be input mode. clr p4m clr p5m mov a, #0ffh ; set all ports to be output mode. b0mov p0m, a b0mov p4m,a b0mov p5m, a b0bclr p4m.0 ; set p4.0 to be input mode. b0bset p4m.0 ; set p4.0 to be output mode.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 79 version 1. 5 7.3 i/o pull up register the i/o pins build in internal pull - up resistors and only support i/o input mode. the port internal pull - up resistor is programmed by pnur register. when the bit of pnur register is 0 , the i/ o pin ? s pull - up is disabled. when the bit of pnur register is 1 , the i/o pin ? s pull - up is enabled. 0 e 0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 0 ur - - p 05 r p 04 r - p 02 r p 01 r p 00 r read/write - - w w - w w w after reset - - 0 0 - 0 0 0 0 e 1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 1 ur p 17 r p 16 r p 15 r p 14 r p 13 r p 12 r p 11 r p 10 r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0 e 4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 4 ur p 47 r p 46 r p 45 r p 44 r p 43 r p 42 r p 41 r p 40 r re ad/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 0 e 5h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 5 ur p 57 r p 56 r p 55 r p 54 r p 53 r p 52 r p 51 r p 50 r read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 ? note : p0.3 is input only pin and without pull - up resister. the p0ur.3 is undefined. ? example: i/o pull up register mov a, #0ffh ; enable p or t0, 4, 5 pull - up register, b0mov p 0 ur , a ; b0mov p4ur,a b0mov p 5 ur , a
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 80 version 1. 5 7.4 i/o port data regist er 0 d0 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p0 - - p05 p04 p03 p02 p01 p00 read/write - - r/w r/w r r/w r/w r/w after reset - - 0 0 0 0 0 0 0 d 1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 1 p17 p16 p15 p14 p13 p12 p11 p10 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0 d 4h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p 4 p47 p46 p45 p44 p43 p42 p41 p40 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0 d5 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p5 p 57 p 56 p 55 p 54 p 5 3 p 52 p 51 p 50 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 ? note : the p03 keeps 1 when external reset enable by code option. ? example: read data fro m input port. b0mov a, p0 ; read data from port 0 b0mov a, p4 ; read d ata from port 4 b0mov a, p5 ; read data from port 5 ? example: write data to output port. mov a, #0ffh ; write data ffh to all port. b0mov p0, a b0mov p4, a b0mov p5, a ? example: write one bit data to output port. b0bset p4.0 ; set p4.0 and p 5.3 to be 1 . b0bset p5.3 b0bclr p4.0 ; set p4.0 and p5.3 to be 0 . b0bclr p5.3
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 81 version 1. 5 7.5 port 4 adc share pin the port 4 is shared with adc input function and no schmitt trigger structure. only one pin of port 4 can be configured as adc input in the same time by adm register. the other pins of port 4 are digital i/o pins. connect an analog signal to coms digital input pin, especially the analog signal level is about 1/2 vdd will cause extra current leakage. in the power down mode, the above leaka ge current will be a big problem. unfortunate ly, if users connect more than one analog input signal to port 4 will encounter above current leakage situation. p4con is port4 configuration register. write 1 into p4con.n will configure related port 4 pin as pure analog input pin to avoid current leakage. 0aeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 p4con p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit[4:0] p4co n[7:0]: p4.n configuration control bits. 0 = p4.n can be an analog input (adc input) or digital i/o pins. 1 = p4.n is pure analog input, can ? t be a digital i/o pin. ? note : when port 4 .n is general i/o port not adc channel, p4con .n must set to 0 or t he port 4 .n digital i/o signal would be isolated . port 4 adc analog input is controlled by gchs and chsn bits of adm register. if gchs = 0, p4.n is general purpose bi - direction i/o port. if gchs = 1, p4.n pointed by chsn is adc analog signal input pin. 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs avrefh chs2 chs1 chs0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 4 gchs: global channel select bit. 0 = disable ain channel. 1 = enable ain channel. bit 3 avrefh: adc external high reference voltage input pin control bit. 0 = adc high reference voltage is from internal vdd. p4.0 is gpio or ain0 pin. 1 = enable adc external high reference voltage input pin from p4.0. bit[2:0] chs[2 :0]: adc input channels select bit. 000 = ain0, 001 = ain1, 010 = ain2, 011 = ain3, 100 = ain4, 101 = ain5, 110 = ain6, 111 = ain7. ? note : for p4.n general purpose i/o function, users should make sure of p4.n s adc channel is disabled, or p4.n is automa tically set as adc analog input when gchs = 1 and chs[2:0] point to p4.n.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 82 version 1. 5 ? example: set p4.1 to be general purpose input mode. p4con.1 must be set as 0 . ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.1 (chs[2:0] = 001b), set gchs=0 ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.1 ; enable p4.1 digital function. ; enable p4.1 input mode. b0bclr p4m.1 ; set p4.1 as input mode. ? example: set p4.1 to be general purpose output. p4con.1 must be set as 0 . ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.1 (chs[2:0] = 001b), set gchs=0. ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.1 ; enable p4.1 digital fun ction. ; set p4.1 output buffer to avoid glitch. b0bset p4.1 ; set p4.1 buffer as 1 . ; or b0bclr p4.1 ; set p4.1 buffer as 0 . ; enable p4.1 output mode. b0bset p4m.1 ; set p4.1 as input mode. p4.0 is shared with general purpose i/o, adc input (ain0) and adc external high reference voltage input. avrefh flag of adm register is external adc high reference voltage input control bit. if avrefh is enabled, p4.0 general purpose i/o and adc analog input (ain0) functions are disabled. p4 .0 pin is connected to adc high reference voltage directly. ? note : for p4.0 general purpose i/o and ain0 functions, avrefh must be set as ? example: set p4.0 to be general purpose input mode. avrefh and p4con.0 bits must be set as 0 . ; check avre fh status. b0bts0 favrefh ; check avrefh = 0. b0bclr favrefh ; avrefh = 1, clear it to disable external adc high reference input. ; avrefh = 0, execute next routine. ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.0 (chs[2:0] = 000b), set gchs=0 ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.0 ; enable p4.0 digital function. ; enable p4.0 input mode. b0bclr p4m.0 ; set p4.0 as input mode.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 83 version 1. 5 ? example: set p4.0 to be general purpose output. evhenb and p4con.0 bits must be set as 0 . ; check avrefh status. b0bts0 favrefh ; check avrefh = 0. b0bclr favrefh ; avrefh = 1, clear it to disable external adc high reference input. ; avre fh = 0, execute next routine. ; check gchs and chs[2:0] status. b0bclr fgchs ;if chs[2:0] point to p4.0 (chs[2:0] = 000b), set gchs=0 ;if chs[2:0] dont dont ; clear p4con. b0bclr p4con.0 ; enable p4.0 digital function. ; set p4.0 output buffer to avoid glitch. b0bset p4.0 ; set p4.0 buffer as 1 . ; or b0bclr p4.0 ; set p4.0 buffer as 0 . ; enabl e p4.0 output mode. b0bset p4m.0 ; set p4.0 as input mode.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 84 version 1. 5 8 8 8 timer s 8.1 watchdog timer the watchdog timer (wdt) is a binary up counter designed for monitoring program execution. if the program g oe s into the unknown status by noise interference, wdt overf low signal raises and resets mcu. watchdog clock controlled by code option and the clock source is internal low - speed oscillator. watchdog overflow time = 8192 / internal low - speed oscillator (sec). vdd internal low rc freq. watchdog overflow time 3v 16khz 512ms 5v 32khz 256ms the watchdog timer has three operating options controlled watchdog code option. ? disable: disable watchdog timer function. ? enable: enable watchdog timer function. watchdog timer actives in normal mode and slow mode. in pow er down mode and green mode, the watchdog timer stops. ? always_on: enable watchdog timer function. the watchdog timer actives and not stop in power down mode and green mode. in high noisy environment, the always_on option of watchdog operations is the strongly recommend ation to make the system reset under error situations and re - start again. watchdog clear is controlled by wdtr register. moving 0x5a data into wdtr is to reset watchdog timer. 0cch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wdtr wdtr7 wdtr6 wdtr5 wdtr4 wdtr3 wdtr2 wdtr1 wdtr0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 ? example : an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: mov a, #5ah ; clear the watchdog timer . b0mov wdtr, a ? example : clear watchdog timer by @rst_wdt macro of sonix ide. main: @rst_wdt ; clear the watchdog timer .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 85 version 1. 5 watchdog timer application note is as following. ? before clearing watchdog timer, check i/o status and check ram contents can improve system error. ? don?t clear watchdog timer in interrupt vector and interrupt service routine. that can improve main routine fail. ? clearing watchdog timer program is only at one part of the program. this way is the best structure to enhance the watchdog timer function. ? example : an operation of watchdog timer is as following. to clear the watchdog timer counter in the top of the main routine of the program. main: don?t mov a, #5ah ; clear the watchdog timer . b0mov wdtr, a call sub1 call sub2
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 86 version 1. 5 8.2 t0 8 - bit basic timer 8.2.1 overview the t0 timer is an 8 - bit binary up timer with basic timer function. the basic timer function supports flag indicator (t0irq bit) and interrupt operation (interrupt vector). the interval time is programmable through t0m, t0c registers and supports rtc function . the t0 builds in green mode w ake - up function. when t0 timer overflow occurs under green mode, the system will be waked - up to last operating mode. ? 8 - bit programmable up counting timer: generate time - out at specific time intervals based on the selected clock frequency. ? interrupt funct ion: t0 timer function supports interrupt function. when t0 timer occurs overflow, the t0irq actives and the system points program counter to interrupt vector to do interrupt sequence. ? rtc function: t0 supports rtc function . t he rtc clock source is from e xternal low speed 32k oscillator when t0tb=1. rtc function is only available in high_clk code option = "ihrc_rtc" . ? green mode function: t0 timer keeps running in green mode and wake s up system when t0 timer overflows. ? note: in rtc mode, the t0 interval time is fixed at 0.5 sec and t0c is 256 counts. f c p u t 0 r a t e ( f c p u / 2 ~ f c p u / 2 5 6 ) t 0 e n b c p u m 0 , 1 t 0 c 8 - b i t b i n a r y u p c o u n t i n g c o u n t e r t 0 e n b r t c t 0 t b l o a d t 0 c v a l u e b y p r o g r a m . t 0 i r q i n t e r r u p t f l a g ( t 0 t i m e r o v e r f l o w . )
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 87 version 1. 5 8.2.2 t0 timer operation t0 timer is controlled by t0 enb bit. when t0 enb= 0 , t0 timer stops. when t0enb=1, t0 timer starts to count. t0c increases 1 by timer clock source. when t0 overflow event occurs, t0irq flag is set as 1 to indicate overflow and cleared by program. the overflow condition is t0c count from full scale (0xff) to zero scale (0x00). t0 doesn ? t build in double buffer, so load t0c by program when t0 timer overflo ws to fix the correct interval time. if t0 timer interrupt function is enabled (t0ien=1), the system will execute interrupt procedure. the interrupt procedure is system program counter points to interrupt vector (org 8) and executes interrupt service routi ne after t0 overflow occurrence. clear t0irq by program is necessary in interrupt procedure. t0 timer can works in normal mode, slow mode and green mode. in green mode, t0 keeps counting, set t0irq and wakes up system when t0 timer overflows. t0 clock source is fcpu (instruction cycle) through t0 rate[2:0] pre - scaler to decide fcpu/2~fcpu/256. t0 length is 8 - bit (256 steps), and the one count period is each cycle of input clock. t0 rate[2:0] t0 clock t0 interval time fhosc= 16mhz, fcpu=fhosc/ 4 fhosc=4mhz, fcpu=fhosc/4 ihrc_rtc mode max. (ms) unit (us) max. (ms) unit (us) max. ( sec ) unit ( ms ) 000b fcpu/ 256 16.384 64 65.536 256 - - 001b fcpu/ 128 8.192 32 32.768 128 - - 010b fcpu/ 64 4.096 16 16.384 64 - - 011b fcpu/ 32 2 .048 8 8.192 32 - - 100b fcpu/ 16 1.024 4 4. 096 1 6 - - 101b fcpu/ 8 0.512 2 2.048 8 - - 110b fcpu/ 4 0.256 1 1.024 4 - - 111b fcpu/ 2 0.128 0.5 0.512 2 - - - 32768hz/64 - - - - 0.5 1.953 0 x 0 0 o r n b y p r o g r a m . . . . . . c l o c k s o u r c e t 0 c t 0 i r q t 0 t i m e r o v e r f l o w s . t 0 i r q s e t a s 1 . r e l o a d t 0 c b y p r o g r a m . t 0 i r q i s c l e a r e d b y p r o g r a m . 0 x 0 1 o r n + 1 0 x f e 0 x f f . . . . . . 0 x 0 0 o r n b y p r o g r a m 0 x 0 2 o r n + 2 0 x 0 2 o r n + 2
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 88 version 1. 5 8.2.3 t0m mode register t0 m is t0 timer mode control register to confi gure t0 operating mode including t0 pre - scaler, clock source these configurations must be setup completely before enabling t0 timer. 0 d8 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0m t0enb t0rate2 t0rate1 t0rate0 - - - t0tb read/write r/w r/w r/ w r/w - - - r/w after reset 0 0 0 0 - - - 0 bit 0 t0tb: rtc clock source control bit. 0 = disable rtc (t0 clock source from fcpu). 1 = enable rtc. bit [6:4] t0 rate[2:0]: t0 timer clock source select bits. 000 = fcpu/ 256 , 001 = fcpu/ 128 , 010 = fcpu/ 6 4 , 011 = fcpu/ 32 , 100 = fcpu/ 16 , 101 = fcpu/ 8 , 110 = fcpu/ 4 , 111 = fcpu/ 2 . bit 7 t0enb: t0 counter control bit. 0 = d isable t0 timer. 1 = enable t0 timer . ? note: t0rate is not available in rtc mode. the t0 interval time is fixed at 0.5 sec. 8.2.4 t0c c ounting register t0c is t0 8 - bit counter. when t0c overflow occurs, the t0irq flag is set as 1 and cleared by program. the t0c decides t0 interval time through below equation to calculate a correct value. it is necessary to write the correct value to t0c register, and then enable t0 timer to make sure the first cycle correct. after one t0 overflow occurs, the t0c register is loaded a correct value by program. 0 d 9h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t0c t0c7 t0c6 t0c5 t0c4 t0c3 t0c2 t0c1 t0 c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t0c initial value is as following. t0c initial value = 256 - (t0 interrupt interval time * t0 clock rate ) ? example: to calculation t0c to obtain 10ms t0 inte rval time. t0 clock source is fcpu = 4mhz/4 = 1mhz. select t0rate=001 (fcpu/128). t0 interval time = 10ms. t0 clock rate = 4 mhz/ 4 /128 t0 c initial value = 256 - (t0 interval time * input clock) = 256 - (10ms * 4mhz / 4 / 128 ) = 256 - ( 10 - 2 * 4 * 10 6 / 4 / 128 ) = b2h ? note: in rtc mode, t0c is 256 counts and generatest0 0.5 sec interval time. don t change t0c value in rtc mode.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 89 version 1. 5 8.2.5 t0 timer operation explame ? t0 timer configuration : ; reset t0 timer. mov a, #0x00 ; clear t0 m register. b0mov t0 m, a ; set t0 clock source and t0 rate. mov a, #0 nnn 0 0 00b b0mov t0 m, a ; set t0 c register for t0 interval time. mov a, # value b0mov t0 c, a ; clear t0 irq b0bclr f t0 irq ; enable t0 timer and interrupt function. b0bset ft0ien ; enable t0 interrupt function. b0bset ft0enb ; enable t0 timer. ? t0 works in rtc mode : ; reset t0 timer. mov a, #0x00 ; clear t0 m register. b0mov t0 m, a ; set t0 rtc function. b0bset ft0tb ; clear t0 c. clr t0c ; c lear t0 irq b0bclr f t0 irq ; enable t0 timer and interrupt function. b0bset ft0ien ; enable t0 interrupt function. b0bset ft0enb ; enable t0 timer.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 90 version 1. 5 8.3 tc0 8 - bit timer/counter 8.3.1 overview the tc0 timer is an 8 - bit binary up timer with basic time r, event counter , buzzer and pwm functions. the basic timer function supports flag indicator (tc0irq bit) and interrupt operation (interrupt vector). the interval time is programmable through tc0m, tc0c, tc0r registers. the event counter is changing tc0 cl ock source from system clock (fcpu) to external clock like signal (e.g. continuous pulse, r/c type oscillating signal ) . tc0 becomes a counter to count external clock number to implement measure application . tc0 also builds in buzzer and pwm functions. the cycle/resolution of buzzer and pwm are controlled by tc0 timer clock rate and tc0r registers, so the buzzer and pwm with good flexibility to implement ir carry signal, motor control and brightness adjuster the main purposes of the tc0 timer are as followi ng. ? 8 - bit programmable up counting timer: generate time - out at specific time intervals based on the selected clock frequency. ? interrupt function: t c0 timer function support s interrupt function. when t c0 timer occurs overflow, the t c0 irq actives and the s ystem points program counter to interrupt vector to do interrupt sequence. ? event counter: the event counter function counts the external clock counts. ? pwm output : the pwm is duty/cycle programmable controlled by t0rate and tc0 r registers. ? buzzer output : the buzzer output signal is 1/2 cycle of tc0 interval time. ? green mode function: all tc0 functions (timer, pwm, buzzer, event counter, auto - reload) keep running in green mode and no wake - up function. f c p u t c 0 r a t e ( f c p u / 2 ~ f c p u / 2 5 6 ) i n t 0 ( s c h m i t t e r t r i g g e r ) t c 0 c k s t c 0 e n b c p u m 0 , 1 t c 0 c 8 - b i t b i n a r y u p c o u n t i n g c o u n t e r t c 0 r r e l o a d d a t a b u f f e r u p c o u n t i n g r e l o a d v a l u e t c 0 t i m e o u t c o m p a r e a l o a d 0 r s t c 0 t i m e o u t a u t o . r e l o a d t c 0 / 2 b u z z e r i n t e r n a l p 5 . 4 i / o c i r c u i t p 5 . 4 p w m p w m 0 o u t t c 0 o u t a l o a d 0 , t c 0 o u t l o a d
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 91 version 1. 5 8.3.2 tc0 timer operation t c0 timer is controlled by tc0enb bit. when tc0enb= 0 , tc0 timer stops. when tc0enb=1, tc0 timer starts to count. before enabling tc0 timer, setup tc0 timer ? s configurations to select timer function modes, e.g. basic timer, interrupt function tc0c increases 1 by timer clock source. when tc0 overflow event occurs, tc0irq flag is set as 1 to indicate overflow and cleared by program. the overflow condition is tc0c count from full scale (0xff) to zero scale (0x00). in difference function modes, tc0c value rel ates to operation. if tc0c value changing effects operation, the transition of operations would make timer function error. so tc0 builds in double buffer to avoid these situations happen. the double buffer concept is to flash tc0c during tc0 counting, to s et the new value to tc0r (reload buffer), and the new value will be loaded from tc0r to tc0c after tc0 overflow occurrence automatically. in the next cycle, the tc0 timer runs under new conditions, and no any transitions occur. the auto - reload function is controlled by aload0 bit in timer/counter mode, and enabled automatically in pwm mode as tc0 enables. if tc0 timer interrupt function is enabled (tc0ien=1), the system will execute interrupt procedure. the interrupt procedure is system program counter poin ts to interrupt vector (org 8) and executes interrupt service routine after tc0 overflow occurrence. clear tc0irq by program is necessary in interrupt procedure. tc0 timer can works in normal mode, slow mode and green mode. but in green mode, tc0 keep coun ting, set tc0irq and outputs pwm, but can ? t wake - up system. tc0 provides different clock sources to implement different applications and configurations. tc0 clock source includes fcpu (instruction cycle) and external input pin (p0.0) controlled by tc0cks bits . tc0cks bit selects the clock source is from fcpu or external input pin . if tc0cks=0, tc0 clock source is fcpu through tc0rate[2:0] pre - scaler to decide fcpu/2~fcpu/256. if tc0cks=1, tc0 clock source is external input pin that means to enable event counter fu nction . tc0rate[2:0] pre - scaler is unless when tc0cks=1 condition. tc0 length is 8 - bit (256 steps) when pwm disabled, and the one count period is each cycle of input clock. tc0rate[2:0] tc0 clock tc0 interval time fhosc=16mhz, fcpu=fhosc/ 4 fhosc=4mhz, fcpu=fhosc/4 max. (ms) unit (us) max. (ms) unit (us) 000b fcpu/ 256 16.384 64 65.536 256 001b fcpu/128 8.192 32 32.768 128 010b fcpu/64 4.096 16 16.384 64 011b fcpu/32 2.048 8 8.192 32 100b fcpu/16 1.024 4 4.0 96 1 6 101b fcpu/8 0.512 2 2.048 8 110b fcpu/4 0.256 1 1.024 4 111b fcpu/2 0.128 0.5 0.512 2 0 x 0 0 o r t c 0 r . . . . . . c l o c k s o u r c e t c 0 c t c 0 i r q t c 0 t i m e r o v e r f l o w s . t c 0 i r q s e t a s 1 . r e l o a d t c 0 c f r o m t c 0 r a u t o m a t i c a l l y . t c 0 i r q i s c l e a r e d b y p r o g r a m . 0 x 0 1 0 x 0 2 0 x 0 3 0 x f e 0 x f f t c 0 r . . . . . .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 92 version 1. 5 8.3.3 tc0m mode register tc0m is tc0 timer mode control register to configure tc0 operating mode including tc0 pre - scaler, clock source, pwm function these confi gurations must be setup completely before enabling tc0 timer. 0 da h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0m tc0enb tc0rate2 tc0rate1 tc0rate0 tc0cks aload0 tc0out pwm0out read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 0 pwm0out: pwm output control bit. 0 = disable pwm output function, and p5.4 is gpio mode. 1 = enable pwm output function, and p5.4 outputs pwm signal. pwm duty controlled by tc0out, aload0 bits. bit 1 tc0out: tc0 time out toggle signal output control bit. only valid when pwm0out = 0. 0 = disable, p5.4 is i/o function . 1 = enable, p5.4 is output tc0out signal. bit 2 aload0: auto - reload control bit. only valid when pwm0out = 0. 0 = disable tc0 auto - reload function. 1 = enable tc0 auto - reload function. bit 3 tc0cks: tc0 clock source select bit. 0 = internal clock ( fcpu ). 1 = external input pin (p0.0/int0) and enable event counter function. tc0rate[2:0] bits are useless. bit [6:4] tc0rate [2:0] : tc0 internal clock select bits. 000 = fcpu/ 2 56 , 001 = fcpu/ 128 , 010 = fcpu/ 64 , 011 = fcpu/ 32 , 100 = fcpu/ 16 , 101 = fcpu/ 8 , 110 = fcpu/ 4 , 111 = fcpu/ 2 . bit 7 t c 0enb: t c 0 counter control bit. 0 = d isable tc0 timer. 1 = enable tc0 timer . 3. note: when tc0cks=1, tc0 became an external event counter and tc0rate is useless. no more p0.0 interrupt request will be raised. (p0.0irq will be always 0) .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 93 version 1. 5 8.3.4 tc0c counting register tc0c is tc0 8 - bit counter. when tc0c overflow occurs, the tc0irq flag is set as 1 and cleared by program. the tc0c decides t c0 interval time through below equation to calculate a correct value. it is necessary to write the correct value to tc0c register and tc0r register first time, and then enable tc0 timer to make sure the fist cycle correct. after one tc0 overflow occurs, th e tc0c register is loaded a correct value from tc0r register automatically, not program. 0 db h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0c tc0c7 tc0c6 tc0c5 tc0c4 tc0c3 tc0c2 tc0c1 tc0c0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the equation of t c 0c initial value is as following. t c 0c initial value = n - (t c 0 interrupt interval time * tc0 clock rate ) n is tc0 overflow boundary number. tc0 timer overflow time has five types (tc0 timer, tc0 event counter, tc0 fcpu clock source, pwm mode and no pwm mode). these parameter s decide tc0 overflow time and valid value as follow table. tc0cks pwm0 aload0 tc0out n tc0c valid value tc0c value binary type remark 0 0 x x 256 0x00~0xff 00000000b~11111111b overflow per 256 cou nt 1 0 0 256 0x00~0xff 00000000b~11111111b overflow per 256 count 1 0 1 64 0x00~0x3f xx000000b~xx111111b overflow per 64 count 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b overflow per 32 count 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b overflow per 16 count 1 - - - 256 0x00~0xff 00000000b~11111111b overflow per 256 count
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 94 version 1. 5 8.3.5 tc0 r auto - reload register tc0 timer builds in auto - reload function, and tc0r register stores reload data. when tc0c overflow occurs, tc0c register is loaded data from tc0r register auto matically. under tc0 timer counting status, to modify tc0 interval time is to modify tc0r register, not tc0c register . n ew tc0c data of tc0 interval time will be updated after tc0 timer overflow occurrence, tc0r loads new value to tc0c register. but at the first time to setup tc0m, tc0c and tc0r must be set the same value before enabling tc0 timer. tc0 is double buffer design. if new tc0r value is set by program, the new value is stored in 1 st buffer. until tc0 overflow occurs, the new value moves to real t c0r buffer. this way can avoid any transitional condition to effect the correctness of tc0 interval time and pwm output signal. 0c d h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tc0 r tc0 r 7 tc0 r 6 tc0 r 5 tc0 r 4 tc0 r 3 tc0 r 2 tc0 r 1 tc0 r 0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 the equation of t c 0 r initial value is as following. t c 0 r initial value = 256 - (t c 0 interrupt interval time * tc0 clock rate ) n is tc0 overflow boundary number. tc0 timer overflow time has five types (tc0 timer , tc0 event counter, tc0 fcpu clock source, pwm mode and no pwm mode). these parameter s decide tc0 overflow time and valid value as follow table. tc0cks pwm0 aload0 tc0out n tc0r valid value tc0r value binary type 0 0 x x 256 0x00~0xff 00000000b~11111111 b 1 0 0 256 0x00~0xff 00000000b~11111111b 1 0 1 64 0x00~0x3f xx000000b~xx111111b 1 1 0 32 0x00~0x1f xxx00000b~xxx11111b 1 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b 1 - - - 256 0x00~0xff 00000000b~11111111b ? example: to calculation tc0c and tc0r value to obtain 10ms tc0 interval time. tc0 clock source is fcpu = 4mhz/4 = 1mhz. select tc0rate=001 (fcpu/128). tc0 interval time = 10ms. tc0 clock rate = 4 mhz/ 4 /128 tc0c/ t c 0 r initial value = 256 - (t c 0 interval time * input clock) = 256 - (10ms * 4mhz / 4 / 128 ) = 256 - ( 10 - 2 * 4 * 10 6 / 4 / 128 ) = b2h
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 95 version 1. 5 8.3.6 tc0 ev ent counter tc0 event counter is set the tc0 clock source from external input pin (p0.0). when tc0cks1=1, tc0 clock source is switch to external input pin (p0.0). tc0 event counter trigger direction is falling edge. when one falling edge occurs, tc0c will up one count. when tc0c counts from 0xff to 0x00, tc0 triggers overflow event. the external event counter input pin?s wake - up function of gpio mode is disabled when tc0 event counter function enabled t o avoid event counter signal trigger system wake - up and not keep in power saving mode. the external event counter input pin?s external interrupt function is also disabled when tc0 event counter function enabled , and the p00irq bit keeps 0 status. the eve nt counter usually is used to measure external continuous signal rate, e.g. continuous pulse, r/c type oscillating signal these signal phase don ? t synchronize with mcu ? s main clock. use tc0 event to measure it and calculate the signal rate in program for d ifferent applications. 8.3.7 tc0 buzzer output the buzzer output is a simple 1/2 duty signal output function. the buzzer signal is generated from tc0 timer. when tc0 timer overflows, the buzzer output exchanges status, and generate s a square waveform. the frequency of buzzer output is 1/2 of tc0 interval time. the tc0 clock has many combination s and easily to make difference frequency. the buzzer output waveform is as following. 0 x 0 0 o r t c 0 r . . . . . . e x t e r n a l i n p u t s i g n e l t c 0 c t c 0 i r q t c 0 t i m e r o v e r f l o w s . t c 0 i r q s e t a s 1 . r e l o a d t c 0 c f r o m t c 0 r a u t o m a t i c a l l y . t c 0 i r q i s c l e a r e d b y p r o g r a m . 0 x 0 1 0 x 0 2 0 x 0 3 0 x f e 0 x f f t c 0 r . . . . . . 0 x f f . . . b u z z e r o u t p u t t c 0 c t c 0 i r q t c 0 t i m e r o v e r f l o w s . t c 0 i r q s e t a s 1 . r e l o a d t c 0 c f r o m t c 0 r a u t o m a t i c a l l y . t c 0 i r q i s c l e a r e d b y p r o g r a m . 0 x 0 0 t c 0 r . . . . . . 0 x f f 0 x 0 0 t c 0 r . . . 0 x f f 0 x 0 0 t c 0 r . . . . . . . . . t c 0 t i m e r i n t e r v a l t i m e t c 0 b u z z e r o u t p u t r a t e
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 96 version 1. 5 when buzzer outputs, tc0irq still actives as tc0 overflows, and tc0 interrupt function actives as tc0ien = 1. but strongly recommend be careful to use buzzer and tc0 timer together, and make sure both functions work well. the buzzer output pin is shared with gpio and switch t o output buzzer signal as tc0out=1 automatically. if tc0out bit is cleared to disable buzzer signal, the output pin exchanges to last gpio mode automatically. it easily to implement carry signal on/off operation, not to control tc0enb bit. 4. note: because the tc0out decides the pwm cycle in pwm mode. the pwm0out bit must be 0 when buzzer output function works. 8.3.8 pulse width modulation (pwm) the pwm is duty/cycle programmable design to offer various pwm signals. when tc0 timer enables and pwm0out bit sets as 1 (enable pwm output), the pwm output pin (p5.4) outputs pwm signal. one cycle of pwm signal is high pulse first, and then low pulse outputs. tc0rate[2:0] bits control the cycle of pwm, aload0 and tc0out bits decides the resolution of pwm, and tc0r decides the duty (high pulse width length) of pwm. tc0c initial value is zero when tc0 timer enables and tc0 timer overflows. when tc0c count is equal to tc0r, the pwm high pulse finishes and exchanges to low level. when tc 0 overflows (tc0c counts from 0xff to 0x00), one complete pwm cycle finishes. the pwm exchanges to high level for next cycle. the pwm is auto - reload design to load tc0r when tc0 overflows and the end of pwm ? s cycle, to keeps pwm continuity. if modify the p wm duty by program as pwm outputting , the new duty occurs at next cycle when tc0r loaded from the reload buffer. b u z z e r o u t p u t t c 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s b u z z e r s i g n a l a u t o m a t i c a l l y . t c 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t l o w ) . t c 0 o u t = 1 . t c 0 o u t = 0 . b u z z e r o u t p u t t c 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t h i g h ) . t c 0 o u t = 1 . t c 0 o u t = 0 . b u z z e r o u t p u t t c 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( i n p u t ) . t c 0 o u t = 1 . t c 0 o u t = 0 . h i g h i m p e n d e n c e ( f l o a t i n g ) t c 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s b u z z e r s i g n a l a u t o m a t i c a l l y . t c 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s b u z z e r s i g n a l a u t o m a t i c a l l y . 0 x 0 0 0 x 0 1 0 x 0 2 t c 0 c . . . t c 0 r - 1 t c 0 r t c 0 r + 1 p w m o u t p u t . . . 0 x f d 0 x f e 0 x f f 0 x 0 0 0 x 0 1 0 x 0 2 . . . e n a b l e t c 0 a n d p w m . t c 0 c c o u n t s f r o m 0 x 0 0 . p w m o u t p u t s h i g h s t a t u s . t c 0 c = t c 0 r . p w m e x c h a n g e s t o l o w s t a t u s . t c 0 c o v e r f l o w s f r o m 0 x f f t o 0 x 0 0 . t c 0 c c o u n t s f r o m 0 x 0 0 . p w m e x c h a n g e s t o h i g h s t a t u s . o n e c o m p l e t e c y c l e o f p w m . n e x t c y c l e .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 97 version 1. 5 the resolution of pwm includes 1/256, 1/64, 1/32, 1/16 controlled by aload0 and tc0out bits to implement high speed pwm signal. aload0, tc0out = 00, the pwm resolution is 1/256. aload0, tc0out = 01, the pwm resolution is 1/64. aload0, tc0out = 10, the pwm resolution is 1/32. aload0, tc0out = 11, the pwm resolution is 1/16. if modify the pwm resolution, the tc0r pw m duty control range must be modified to meet resolution. when pwm outputs, tc0irq still actives as tc0 overflows, and tc0 interrupt function actives as tc0ien = 1. but strongly recommend be careful to use pwm and tc0 timer together, and make sure both fun ctions work well. aload0 tc0out pwm resolution tc0r valid value tc0r value binary type 0 0 256 0x00~0xff 00000000b~11111111b 0 1 64 0x00~0x3f xx000000b~xx111111b 1 0 32 0x00~0x1f xxx00000b~xxx11111b 1 1 16 0x00~0x0f xxxx0000b~xxxx1111b the pwm output pin is shared with gpio and switch to output pwm signal as pwm0out=1 automatically. if pwm0out bit is cleared to disable pwm, the output pin exchanges to last gpio mode automatically. it easily to implement carry signal on/o ff operation, not to control tc0enb bit. 1 / 2 5 6 d u t y 1 / 6 4 d u t y 1 / 3 2 d u t y 1 / 1 6 d u t y p w m o u t p u t p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t l o w ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . p w m o u t p u t p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( o u t p u t h i g h ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . p w m o u t p u t p w m 0 o u t = 1 . t h e p i n e x c h a n g e s t o o u t p u t m o d e a n d o u t p u t s p w m s i g n a l a u t o m a t i c a l l y . p w m 0 o u t = 0 . t h e p i n e x c h a n g e s t o l a s t g p i o m o d e ( i n p u t ) . p w m 0 o u t = 1 . p w m 0 o u t = 0 . h i g h i m p e n d e n c e ( f l o a t i n g )
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 98 version 1. 5 8.3.9 tc0 timer operation explame ? tc0 timer configuration : ; reset tc0 timer. mov a, #0x00 ; clear tc0m register. b0mov tc0m, a ; set tc0 rate and auto - reload function . mo v a, #0 nnn 0 00 0b ; tc0rate[2:0] bits. b0mov tc0m, a b0bset faload0 ; set tc0c and tc0r register for tc0 interval time. mov a, # value ; tc0c must be equal to tc0r. b0mov tc0c, a b0mov tc0r, a ; clear tc0irq b0bclr ftc0irq ; enable tc0 timer and interrupt function. b0bset ftc0ien ; enable tc0 interrupt function. b0bset ftc0enb ; enable tc0 timer. ? tc0 event counter configuration : ; reset tc0 timer. mov a, #0x00 ; clear tc0m register. b0mov tc0m, a ; set tc0 auto - reload function . b0bset faload0 ; enable tc0 event counter . b0bset ftc0cks ; set tc0 clock source from external input pin (p0.0). ; set tc0c and tc0r register for tc0 interval time. mov a, # value ; tc0c must be equal to tc0r. b0mov tc0c, a b0mov tc0r, a ; clear tc0irq b0bclr ftc0irq ; enable tc0 timer and interrupt function. b0bset ftc0ien ; enable tc0 interrupt function. b0bset ftc0enb ; enable tc0 timer.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 99 version 1. 5 ? tc0 buzzer output configuration : ; res et tc0 timer. mov a, #0x00 ; clear tc0m register. b0mov tc0m, a ; set tc0 rate and auto - reload function . mov a, #0 nnn 0 00 0b ; tc0rate[2:0] bits. b0mov tc0m, a b0bset faload0 ; set tc0c and tc0r register for tc0 interval time. m ov a, # value ; tc0c must be equal to tc0r. b0mov tc0c, a b0mov tc0r, a ; enable tc0 timer and buzzer output function. b0bset ftc0enb ; enable tc0 timer. b0bset ftc0out ; enable tc0 buzzer output function. ? tc0 pwm configuration : ; reset tc0 timer. mov a, #0x00 ; clear tc0m register. b0mov tc0m, a ; set tc0 rate for pwm cycle . mov a, #0 nnn 0 0 00b ; tc0rate[2:0] bits. b0mov tc0m, a ; set pwm resolution . mov a, #00 0 0 0 nn 0b ; aload0 and tc0out bits. or tc0m, a ; set tc0r register for pwm duty . mov a, # value b0mov tc0r, a ; clear tc0c as initial value . clr tc0c ; enable pwm and tc0 timer . b0bset ftc0enb ; enable tc0 timer. b0bset fpwm0out ; enable pwm.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 100 version 1. 5 8.4 t1 16 - bit timer/counter 8.4.1 over view the t1 timer is a 16 - bit binary up timer with basic timer and capture timer functions. the basic timer function supports flag indicator (t1irq bit) and interrupt operation (interrupt vector). the interval time is programmable through t1m, t1ch/t1cl 16 - bit counter registers. the capture timer supports high pulse width measurement, low pulse width measurement and cycle measurement from p0.0 and comparator output oscillating like signal (e.g. continuous pulse, r/c type oscillating signal ) . t1 becomes a t imer meter to count external signal time parameters to implement measure application . the main purposes of the t1 timer are as following. ? 16 - bit programmable up counting timer: generate time - out at specific time intervals based on the selected clock freq uency. ? interrupt function: t1 timer function support s interrupt function. when t1 timer occurs overflow, the t1 irq actives and the system points program counter to interrupt vector to do interrupt sequence. ? 16 - bit capture timer: measure the input signal pulse width and cycle depend on the t1 clock time base to decide the capture timer?s resolution. the capture timer builds in programmable trigger edge selection to decide the start - stop trigger event. ? green mode function: t 1 timer keep s running in green m ode and wake s up system when t1 timer overflows and issue t1irq=1 . t 1 e n b c p u m 0 , 1 t 1 c h , l 1 6 - b i t b i n a r y u p c o u n t i n g c o u n t e r t 1 i r q i n t e r r u p t f l a g ( t 1 t i m e r o v e r f l o w . ) ( c a p t u r e t i m e r s t o p ) c p t g [ 1 : 0 ] = 0 0 , d i s a b l e . 0 1 / 1 0 / 1 1 = e n a b l e . t 1 c h b u f f e r t 1 c l b u f f e r w r i t e t 1 c l r e g i s t e r r e a d t 1 c l r e g i s t e r c p t g [ 1 : 0 ] c p t c k s p 0 . 0 / i n t 0 c o m p a r a t o r 0 f c p u t 1 r a t e ( f c p u / 1 ~ f c p u / 1 2 8 )
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 101 version 1. 5 8.4.2 t1 timer operation t1 timer is controlled by t1 enb bit. when t1 enb= 0 , t1 timer stops. when t1enb=1, t1 timer starts to count. before enabling t1 timer, setu p t1 timer ? s configurations to select timer function modes, e.g. basic timer, interrupt function t1 16 - bit counter (t1ch, t1cl) increases 1 by timer clock source. when t1 overflow event occurs, t1irq flag is set as 1 to indicate overflow and cleared by program. the overflow condition is t1ch, t1cl count from full scale (0xffff) to zero scale (0x0000). t1 doesn ? t build in double buffer, so load t1ch, t1cl by program when t1 timer overflows to fix the correct interval time. if t1 timer interrupt function is enabled (t1ien=1), the system will execute interrupt procedure. the interrupt procedure is system program counter points to interrupt vector (org 8) and executes interrupt service routine after t1 overflow occurrence. clear t1irq by program is necessary in interrupt procedure. t1 timer can works in normal mode, slow mode and green mode. in green mode, t1 keeps counting, set t1irq and wakes up system when t1 timer overflows. t1 clock source is fcpu (instruction cycle) throug h t 1 rate[2:0] pre - scaler to decide fcpu/1~fcpu/128. t1 length is 16 - bit (65536 steps), and the one count period is each cycle of input clock. t1 rate[2:0] t1 clock t1 interval time fhosc=16mhz, fcpu=fhosc/ 4 fhosc=4mhz, fcpu=fhosc/4 max. (ms) unit (us) max. (ms) unit (us) 000b fcpu/128 2097.152 32 8388.608 128 001b fcpu/64 1048.576 16 4194.304 64 010b fcpu/32 524.288 8 2097.152 32 011b fcpu/16 262.144 4 1048.576 1 6 100b fcpu/8 131.072 2 524.288 8 101b fcpu/4 65.536 1 262.144 4 110b fcpu/2 32 .768 0.5 131.072 2 111b fcpu/1 16.384 0.25 65.536 1 0 x 0 0 0 0 o r n b y p r o g r a m . . . . . . c l o c k s o u r c e t 1 c h , t 1 c l t 1 i r q t 1 t i m e r o v e r f l o w s . t 1 i r q s e t a s 1 . r e l o a d t 1 c h , t 1 c l b y p r o g r a m . t 1 i r q i s c l e a r e d b y p r o g r a m . 0 x 0 0 0 1 o r n + 1 0 x f f f e 0 x f f f f . . . . . . 0 x 0 0 0 0 o r n b y p r o g r a m 0 x 0 0 0 2 o r n + 2 0 x 0 0 0 2 o r n + 2
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 102 version 1. 5 8.4.3 t1m mode register t1 m is t1 timer mode control register to configure t1 operating mode including t1 pre - scaler, clock source, capture parameters these configurations must be setup completely before enabling t1 timer. 0a0h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1 m t1 enb t1 rate2 t1 rate1 t1 rate0 cptcks cptstart cptg1 cptg0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit [1:0] cptg[1:0]: t1 capture timer functi on control bit. 00 = disable capture timer function. 01 = high pulse width measurement. 10 = low pulse width measurement 11 = cycle measurement . bit 2 cptstart : t1 capture timer operating control bit. 0 = process end . 1 = start to count and processin g . bit 3 cpt cks: t1 capture timer input source select bit. 0 = external input pin (p0.0/int0) and enable capture timer function. 1 = comparator output terminal and enable capture timer function. bit [6:4] t1 rate[2:0]: t1 timer clock source select bit s. 000 = fcpu/128, 001 = fcpu/64, 010 = fcpu/32, 011 = fcpu/16, 100 = fcpu/8, 101 = fcpu/4, 110 = fcpu/2 , 111 = fcpu/1. bit 7 t1enb: t1 counter control bit. 0 = d isable t1 timer. 1 = enable t1 timer .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 103 version 1. 5 8.4.4 t1c h, t1cl 16 - bit counting register s t1 counter is 16 - bit counter combined with t1ch and t1cl registers. when t1 timer overflow occurs, the t1irq flag is set as 1 and cleared by program. the t1ch, t1cl decide t1 interval time through below equation to calculate a correct value. it is necessary to writ e the correct value to t1ch and t1cl registers, and then enable t1 timer to make sure the fist cycle correct. after one t1 overflow occurs, the t1ch and t1cl registers are loaded correct value s by program. 0a1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 b it 0 t1c l t1c l 7 t1c l 6 t1c l 5 t1c l 4 t1c l 3 t1c l 2 t1c l 1 t1c l 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 0a2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 t1ch t1ch 7 t1ch 6 t1ch 5 t1ch 4 t1ch 3 t1ch 2 t1ch 1 t1ch 0 read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 the t1 timer counter length is 16 - bit and points to t1ch and t1cl registers. the timer counter is double buffer design. the core bus is 8 - bit, so access 16 - bit data needs a latch flag to avoid the transient status affect the 16 - bit data mistake occurrence. under write mode, the write t 1c l is the latch control flag. under read mode, the read t1cl is the latch control flag. so, write t1 16 - bit counter is to write t 1 ch first, and then write t1cl. the 16 - bit data is written to 16 - bit counter buffer after executing writing t 1 cl. read t1 16 - bit counter is to read t 1 cl first, and then read t 1 ch. the 16 - bit data is dumped to t 1 ch / t 1 cl after executing reading t 1 cl. ? read t1 counter buffer sequence is to rea d t1cl first, and then read t1ch. ? write t1 counter buffer sequence is to write t1ch first, and then write t1cl. the equation of t1 16 - bit counter (t1ch, t1cl) initial value is as following. t1c h, t1cl initial value = 65536 - (t1 interrupt interval t ime * t1 clock rate ) example: to calculation t1ch and t1cl values to obtain 500 ms t1 interval time. t1 clock source is fcpu = 16mhz/16 = 1mhz. select t1rate=000 (fcpu/128). t1 interval time = 500 ms. t1 clock rate = 16mhz/16/128 t1 16 - bit counter init ial value = 65536 - (t1 interval time * input clock) = 65536 - ( 50 0ms * 16mhz / 16 / 128 ) = 65536 - ( 500*10 - 3 * 16 * 10 6 / 16 / 128 ) = f0bdh (t1ch = f 0 h, t1cl = bd h)
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 104 version 1. 5 8.4.5 t1 cpature timer the 16 - bit capture timer purpose is to measure input signal pulse widt h and cycle. the measure ment is through t1 timer by trigger selection. the concept is using t1 to measure input signal like a meter. when trigger condition exists, the t1 timer starts and stops following signal condition. the capture timer is controlled by cptg[1:0] bits. when cptg[1:0] = 00, the capture timer is disabled. when cptg[1:0] = 01/10/11, the capture timer is enabled, but the t1enb must be enabled first . the capture timer can measure input high pulse width, input low pulse width and the cycle of input signal controlled by cptg[1:0]. cptg[1:0] = 01, measure input high pulse width. cptg[1:0] = 10, measure input low pulse width. cptg[1:0] = 11, measure the cycle of input signal. the cptg[1:0] only selects the capture timer function, not execute the c apture timer. cptstart bit is capture timer execution control bit . when cptstart is set as 1, the capture timer waits the right trigger edge to active 16 - bit counter. if t he trigger edge finds , the t1 16 - bit counter starts to count which clock source is t1. when the second right edge finds, the 16 - counter stops, cptstart is cleared and the t1irq actives. before setting cptstart bit, the t1 16 - bit counter is cleared for capture timer initialization automatically. ? high pulse width measurement ( t1enb = 1. cptg[1:0] = 01. ) the high pulse width measurement is using rising edge to trigger t1 timer counting and falling edge to stop t1 timer . if set cptstart bit at high pulse duration, the capture timer will measure next high pulse until the rising edge occurrence. when the falling edge occurs and t1 timer stops, the t1ch, t1cl 16 - bit counter is the period of high pulse width. ? low pulse width measurement ( t1enb = 1. cptg[1:0] = 10. ) the low pulse wi dth measurement is using falling edge to start t1 timer counting and rising edge to stop t1 timer . if set cptstart bit at low pulse duration, the capture timer will measure next low pulse until the falling edge occurrence. when the rising edge occurs and t 1 timer stops, the t1ch, t1cl 16 - bit counter is the period of low pulse width. i n p u t s i g n a l t 1 1 6 - b i t c o u n t e r ( t 1 c h , t 1 c l ) u n - k n o w d a t a 0 x ? ? ? ? 0 x 0 0 0 0 i n i t i a l i z a t i o n 1 2 n - 1 0 x 0 0 0 0 i n i t i a l i z a t i o n n 1 c p t s t a r t = 1 r i s i n g e d g e t 1 s t a r t s t o c o u n t . t 1 i s c o u n t i n g . f a l l i n g e d g e t 1 s t o p s c o u n t i n g . c p t s t a r t = 0 n i s t h e h i g h p u l s e w i d t h p e r i o d . r e a d i t b y p r o g r a m t h r o u g h t 1 c h , t 1 c l r e g i s t e r s . i n p u t s i g n a l u n - k n o w d a t a 0 x ? ? ? ? 0 x 0 0 0 0 i n i t i a l i z a t i o n 1 2 n - 1 0 x 0 0 0 0 i n i t i a l i z a t i o n n 1 c p t s t a r t = 1 f a l l i n g e d g e t 1 s t a r t s t o c o u n t . t 1 i s c o u n t i n g . r i s i n g e d g e t 1 s t o p s c o u n t i n g . c p t s t a r t = 0 n i s t h e l o w p u l s e w i d t h p e r i o d . r e a d i t b y p r o g r a m t h r o u g h t 1 c h , t 1 c l r e g i s t e r s . t 1 1 6 - b i t c o u n t e r ( t 1 c h , t 1 c l )
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 105 version 1. 5 ? input cycle measurement ( t1enb = 1. cptg[1:0] = 11. ) the cycle measurement is using rising edge to start and stop t1 timer . if set cptstart bi t at high or low pulse duration, the capture timer will measure next cycle until the rising edge occurrence. when the rising edge occurs and t1 timer stops, the t1ch, t1cl 16 - bit counter is the cycle width. i n p u t s i g n a l u n - k n o w d a t a 0 x ? ? ? ? 0 x 0 0 0 0 i n i t i a l i z a t i o n 1 2 n - 1 0 x 0 0 0 0 i n i t i a l i z a t i o n n 1 c p t s t a r t = 1 r i s i n g e d g e t 1 s t a r t s t o c o u n t . t 1 i s c o u n t i n g . r i s i n g e d g e t 1 s t o p s c o u n t i n g . c p t s t a r t = 0 n i s t h e c y c l e o f i n p u t s i g n a l . r e a d i t b y p r o g r a m t h r o u g h t 1 c h , t 1 c l r e g i s t e r s . t 1 1 6 - b i t c o u n t e r ( t 1 c h , t 1 c l )
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 106 version 1. 5 8.4.6 t1 timer operation explame ? t1 timer configur ation : ; reset t1 timer. mov a, #0x00 ; clear t1 m register. b0mov t1 m, a ; set t1 clock rate. mov a, #0 nnn 0 0 00b ; t1rate[2:0] bits. b0mov t1 m, a ; set t1 ch, t1cl register s for t1 interval time. mov a, # value 1 ; set high byte firs t. b0mov t1 c h , a mov a, # value 2 ; set low byte. b0mov t1 c l , a ; clear t1 irq b0bclr f t1 irq ; enable t1 timer and interrupt function. b0bset ft1ien ; enable t1 interrupt function. b0bset ft1enb ; enable t1 timer. ? t1 capture timer for single cycle measurement configuration : ; reset t1 timer. mov a, #0x00 ; clear t1 m register. b0mov t1 m, a ; set t1 clock rate , select input source, and select/enable t1 capture timer . mov a, #0 nnn 0 0 mm b ; nnn is t1rate[2:0] for t 1 clock rate selection. b0mov t1 m, a ; mm is cptg[1:0] for t1 capture timer selection. ; cptg[1:0] = 00b, disable t1 capture timer. ; cptg[1:0] = 01b, high pulse width measurement. ; cptg[1:0] = 10b, low pulse width measurement. ; cpt g[1:0] = 11b, cycle measurement. ; select t1 capture source. b0bclr fcptcks ; capture source is p0.0. ; or b0bset fcptcks ; capture source is comparator output. ; clear t1ch, t1cl . clr t1ch ; clear high byte first. clr t1cl ; clea r low byte. ; clear t1 irq b0bclr f t1 irq ; enable t1 timer and interrupt function. b0bset ft1ien ; enable t1 interrupt function. b0bset ft1enb ; enable t1 timer. ; set capture timer start bit. b0bset fcptstart
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 107 version 1. 5 9 9 9 multi - purpos e pulse width modulation (pwm1) 9.1 overview the multi - purpose pulse width modulation (pwm) is a high performance design including programmable high resolution, duty/cycle programmable, high - speed frequency, synchronous trigger function and inverse output fun ction. the pwm resolution is programmable including 8 - bit, 10 - bit and 12 - bit. the pwm cycle is decides by pwm clock source, pwm clock rate selection and pwm resolution. the pwm clock source includes fcpu and fhosc. the pwm clock rate includes fhosc/1~fhosc /128 and fcpu/1~fcpu/128. the pwm uses new technology to implement pwm high speed frequency and reduce the ripple effect of output signal. the inverse output function outputs a complete inverse waveform of normal pwm signal, and also builds in programmable dead - band function. the pwm builds in synchronous trigger function to trigger pwm output. the inverse pwm output with dead - band and synchronous trigger function can implement ac zero - cross processing application. the pwm output pins are shared with gpio p in. the pwm main functions are as following. ? high speed - up pwm. ? 8/10/12 - bits programmable resolution with auto reload buffers. ? multi clock source including f h osc, fcpu. ? inverse output pin with programmable dead - band function. ? non - inverse output pin wi th programmable dead - band function. ? synchronous trigger function is to control pwm output. the trigger source is from comparator or external pin. the trigger edge is programmable including rising, falling and bi - direction. p w 1 r ( p w m 1 2 - b i t r e l o a d b u f f e r ) p w m d u t y 1 2 - b i t c o m p a r a t i v e b u f f e r p w m 1 2 - b i t u p c o u n t i n g c o u n t e r c o m p a r e r s p w 1 l n [ 1 : 0 ] p w 1 l n [ 1 : 0 ] p w m c o u n t e r o v e r f l o w s i g n a l p w m c o u n t e r o v e r f l o w p w m s i g n a l l o w p w 1 s g p i o p w m o u t p u t p w m 1 p i n p w 1 e n p w 1 c k s f h o s c f c p u f p w m p w 1 r a t e [ 2 : 0 ] 1 ~ p w 1 g e n c o m p a r a t o r 0 p w m 1 t e x t e r n a l t r i g g e r p w 1 g s d e a d - b a n d p r o c e s s o r p w 1 n e n p w 1 d e n p w 1 d [ 2 : 0 ] p w 1 n v p w m 1 n p i n p w m p h a s e p r o c e s s o r
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 108 version 1. 5 9.2 pwm 1 common operation the pwm is four phases design. one cycle of pwm is combined from four sub - cycle signals. pwm signal keeps original cycle parameter, but the frequency is faster. t he pwm frequency is equal to sub - cycle ? s frequency. the duty of pwm is placed in each of sub - cycle. the cycle of the above pwm waveform is (t1+t2+t3+t4) / (pwm cycle) . the duty output sequence of the four phases is a special design and more balance. the cycle of pwm is controlled by pwm cloc k source and pwm clock rate options. pw1cks bit selects pwm clock source (f pwm ) from fhosc and fcpu. pw1rate[2:0] bits selects pwm clock rate from f pwm /1~f pwm /128. so the pwm cycle selection is very flexib le. the pwm reload buffers (pw1rh, pw1rl) decide the duty of pwm and through pwm phase processor to allot the duty to each phase. the pwm designs auto - reload function. if modify the pwm duty by program as pwm outputting, the new duty occurs at next cycle and not change immediately. the methods can avoid the transitional duty occurrence . t he pwm resolution includes 8 - bit, 10 - bit and 12 - bit controlled by pw1ln[1:0] bit. pw1ln[1:0]=00 selects 8 - bit pwm. pw1ln[1:0]=01 selects 10 - bit pwm. pw1ln[1:0]=10 selects 12 - bit pwm. the pwm resolution decision depends on application requirement. the pwm output is controlled by pw1 en and pw1 s bits. pw1en bit controls pwm1 pin to be gpio or pwm output pin purpose. when pw1en = 0, pwm1 pin is gpio mode. when pw1en = 1, pwm1 pin changes to pwm output pin and low status fo r initial status. pw1s bit controls to output pwm signal and useable as pw1en = 1. when pw1s = 0, disable pwm signal output, and pwm1 pin keeps initial status. when pw1s = 1, pwm signal outputs to pwm1 pin. ? note: when pw1 s= 1 and pwm starts to output, the first pwm cycle is a complete cycle, and no any delay time or error pwm signal at pw1 s rising edge. 0 x 0 0 0 x 0 1 0 x 3 f 8 - b i t p w m c o u n t e r . . . 0 x 4 0 0 x 4 1 0 x 7 f p w m 1 o u t p u t . . . 0 x 8 0 0 x 8 1 0 x b f 0 x 0 0 0 x 0 1 0 x 0 2 . . . e n a b l e p w m 1 . p w m o u t p u t s h i g h s t a t u s . p w m c o u n t e r o v e r f l o w s . p w m e x c h a n g e s t o h i g h s t a t u s . o n e c o m p l e t e c y c l e o f p w m . n e x t c y c l e . . . . 0 x c 0 0 x c 1 . . . 0 x f f p h a s e 1 p h a s e 2 p h a s e 3 p h a s e 4 t 1 t 2 t 3 t 4 0 x 0 0 0 0 x 0 0 1 0 x 0 f f 1 0 - b i t p w m c o u n t e r . . . 0 x 1 0 0 0 x 1 0 1 0 x 1 f f . . . 0 x 2 0 0 0 x 2 0 1 0 x 2 f f 0 x 0 0 0 0 x 0 0 1 0 x 0 0 2 . . . . . . 0 x 3 0 0 0 x 3 0 1 . . . 0 x 3 f f 0 x 0 0 0 0 x 0 0 1 0 x 3 f f 1 2 - b i t p w m c o u n t e r . . . 0 x 4 0 0 0 x 4 0 1 0 x 7 f f . . . 0 x 8 0 0 0 x 8 0 1 0 x b f f 0 x 0 0 0 0 x 0 0 1 0 x 0 0 2 . . . . . . 0 x c 0 0 0 x c 0 1 . . . 0 x f f f p w 1 e n p w 1 s i n p u t / o u t p u t p w m 1 o u t p u t p i n p w m s i g n a l o u t p u t g p i o s t a t u s g p i o s t a t u s l o w s t a t u s l o w s t a t u s p w m s t a r t t o o u t p u t i n p u t / o u t p u t
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 109 version 1. 5 9.3 inverse pwm1 output with dead - band function the pwm1 builds in inverse output function controlled by pw1nen bit. when pw1 n en = 0, pwm1 n pin is gpio mode. when pw1 n en = 1, pwm1 n pin changes to inverse pwm output pin and used pw1nv bit to select pwm output phase. the pwm signal from pwm1 n pin is decided by pw1nv bit as pw1nen = 1 . when pw1nv = 0, the pw m 1n pin outputs the i nverse pwm signal of pwm1. when pwm1nv = 1, the pw m 1n pin outputs the non - inverse pwm signal of pwm1. the inverse pwm builds in dead - band function. the inverse pwm signal has a delay time of pwm 1 signal. the pwm dead - band function is controlled by pw1den bit. when pw1den = 0, the pwm1 dead - band function is disabled. when pw1den = 1, enable pwm1 dead - ban function . the pw1den is only usable when pwm inverse function enables (pw1nen = 1). the in verse pwm dead - band occurs in pwm1 high pulse width, and the dead - band period is programmable. the dead - band period is symmetrical at left - right terminal of pwm1 high pulse width. if the dead - band period is set as 1*fpwm, 1*fpwm dead - band is in the left s ide of pwm high pulse, and the other side also includes one dead - band duration. so the total dead - band period is 2*fpwm under 1*fpwm dead - band configuration. the dead - band period is controlled by pw1d[2:0] bits ( 000 = 1*fpwm clock. 001 = 2* fpwm clock. 010 = 3* fpwm clock. 011 = 4* fpwm clock. 100 = 5* fpwm clock. 101 = 6* fpwm clock. 110 = 7* fpwm clock. 111 = 8* fpwm clock ) . t o take care the pwm high pulse width with dead - bane function is necessary. recommend the dead - band period less than pwm high pulse width, or the pwm high pulse width disappears. ? note: if the bead band period is longer than pwm duty, the pwm 1n is no output. p w m 1 p w m 1 n ( p w 1 n v = 0 ) p w m 1 n ( p w 1 n v = 1 ) p h a s e 1 p h a s e 2 p h a s e 3 p h a s e 4 p w m c y c l e p w m d u t y p w m 1 p w m 1 n ( p w 1 n v = 0 ) d e a d b a n d d e a d b a n d d e a d b a n d p w m 1 n ( p w 1 n v = 1 )
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 110 version 1. 5 9.4 pwm synchronous trig ger function the pwm1 builds in synchronous trigger function. the trigger source s include mcu ? s compa rator 0 output signal and pw1t external trigger pin. use the trigger to decide pwm signal output or not. actually the pwm synchronous trigger function is to control pw1s bit through the trigger source, not program. the pwm synchronous trigger function is c ontrolled by pw1gen bit. when pw1gen = 0, the pwm synchronous trigger function is disabled. when pw1gen = 1, enable pwm synchronous trigger function . the pwm1 synchronous trigger operation includes 6 types decided through pw 1gd bit and the direction selection of trigger source. pw1gd bit selects pwm operation as trigger occurrence. when pw1ged = 0, disable pwm output as trigger occurrence. when pw1gd = 1, enable pwm output as trigger occurrence. if the trigger edge direction is rising and pw1gd = 0, the pwm operation is stop pwm output as rising edge trigger occurrence. the trigger sources builds in trigger edge options including rising edge, falling edge and bi - direction edge. the rising edge and falling edge are single trig ger function. when the trigger occurrence, pw1s bit is controlled by trigger source and must be set or cleared by program for the other operation. the bi - direction edge enables and disables pw1s bit. when edge trigger occurrence , pw1s bit is enabled/disabl e by first ed ge, and disabled/enabled by second edge automatically. the edge direction is follow trigger source edge configuration. the pw1s is controlled by pwm1 synchronous trigger as below table. pw1gen pw1gd cm0g[1:0] pw1gs=1 p00g[1:0] pw1gs=0 edge d irection pwm synchronous trigger operation pw1s (pwm start bit) 1 0 00 00 no edge. no trigger source. by program 1 0 01 01 rising edge. pwm rising edge disable. 0: edge. 1: program 1 pwm rising edge enable. 0: program 1: edge 0 10 10 fa lling edge. pwm falling edge disable. 0: edge 1: program 1 pwm falling edge enable. 0: program 1: edge 0 11 11 bi - direction. pwm rising edge disable and falling edge enable. 0/1: edge. 1 pwm falling edge disable and rising edge enable. 0/1 : edge. 0 - - - - disable pwm synchronous trigger function. by program p w 1 s p w m 1 o u t p u t p i n p w m s i g n a l o u t p u t l o w s t a t u s l o w s t a t u s r i s i n g e d g e e n a b l e r i s i n g e d g e d i s a b l e f a l l i n g e d g e d i s a b l e f a l l i n g e d g e e n a b l e r i s i n g e d g e e n a b l e f a l l i n g e d g e e n a b l e r i s i n g e d g e d i s a b l e f a l l i n g e d g e d i s a b l e d i s a b l e b y p r o g r a m d i s a b l e b y p r o g r a m e n a b l e b y p r o g r a m e n a b l e b y p r o g r a m r i s i n g e d g e ( p w 1 g d = 0 ) f a l l i n g e d g e ( p w 1 g d = 0 ) r i s i n g e d g e ( p w 1 g d = 1 ) f a l l i n g e d g e ( p w 1 g d = 1 ) b i - d i r e c t i o n ( p w 1 g d = 1 ) b i - d i r e c t i o n ( p w 1 g d = 0 )
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 111 version 1. 5 9.5 pwm 1 mode register pw1m and pw1rh registers pwm1 mode control register s to configure pwm operating mode including pwm pre - scaler, clock source, pwm resolution, pwm synchronous t rigger function these configurations must be setup completely before enabling pwm1 function. 093h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw1m pw1en pw1rate2 pw1rate1 pw1rate0 pw1cks pw1ln1 pw1ln0 pw1s read/write r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 pw1en: pwm1 control bit. 0 = disable. pwm1 ( p 0.1) and pwm1n ( p 0.2) pins are gpio mode. 1 = enable. pwm1 ( p 0.1) is pwm output pin and low status. bit [6:4] pw1rate[2:0]: pwm1 clock divide control bit. note: fpwm is pwm1 clock source. 000 = fpwm/128, 001 = fpwm/64, 010 = fpwm/32, 011 = fpwm/16, 100 = fpwm/8, 101 = fpwm/4, 110 = fpwm/2, 111 = fpwm/1. bit 3 pw1cks: pwm1 clock source select bit. 0 = f h osc. 1 = fcpu. bit [2:1] pw1ln[1:0]: pwm1 resolution select b it. 00 = 8 - bit. 01 = 10 - bit. 10 = 12 - bit. 11 = reserved. bit 0 pw1s: pwm1 start to output control bit. it is controlled by program or pwm synchronous trigger edge. 0 = disable pwm output. pwm1 output pin is low status. 1 = pwm outputting. 096h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw1rh pw1gs pw1gen pw1gd - pw1r11 pw1r10 pw1r9 pw1r8 read/write r/w r/w r/w - r/w r/w r/w r/w after reset 0 0 0 - 0 0 0 0 bit 7 pw1gs: pwm1 synchronous trigger source select bit. the function is workable wh en pwm synchronous trigger function enabled. 0 = pwm1t pin (p0.0). 1 = comparator 0 output signal . bit 6 pw1gen: pwm1 synchronous trigger function control bit. 0 = disable. 1 = enable. bit 5 pw1gd: pwm1 synchronous trigger operation control bi t. 0 = disable pwm output. 1 = enable pwm output.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 112 version 1. 5 090h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw1nm pw1nen pw1d2 pw1d1 pw1d0 pw1den pw1nv - - read/write r/w r/w r/w r/w r/w r/w - - after reset 0 0 0 0 0 0 - - bit 7 pw1nen: pwm1 invert ou tput function control bit. 0 = disable.pwm1n pin is p 0.2 gpio mode. 1 = enable when pw1en = 1. pwm1n pin is pwm1 invert output pin and isolate p 0.2 gpio function. bit [6:4] pw1d[2:0]: pwm1 invert output dead - band period select bit. 000 = 1*fpwm clock. 0 01 = 2* fpwm clock. 010 = 3* fpwm clock. 011 = 4* fpwm clock. 100 = 5* fpwm clock. 101 = 6* fpwm clock. 110 = 7* fpwm clock. 111 = 8* fpwm clock. bit 3 pw1den: pwm1 invert output dead - band control bit. 0 = disable. 1 = enable. bit 2 pw1 nv : pwm1 inv ert output control bit. 0 = pw1n pin outputs the inverse signal with dead - band of pwm1. 1 = pw1n pin output signal direction is equal to pwm1 and with dead - band.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 113 version 1. 5 9.6 pwm1 duty register the duty of pwm1 is decided by pw1rh, pw1rl registers. the length of pw m duty registers is 12 - bit. the operation is base on pwm counter value and pwm phase processor to generate pwm output signal. the pw1rh, pw1rl duty registers build in auto - reload function. i f modify the pwm duty by program as pwm outputting, the new duty o ccurs at next cycle and not change immediately. the methods can avoid the transitional duty occurrence. 096h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw1rh pw1gs pw1gen pw1gd - pw1r11 pw1r10 pw1r9 pw1r8 read/write r/w r/w r/w - r/w r/w r/w r/w after reset 0 0 0 - 0 0 0 0 bit [3:0] pw1r [11:8] = pwm1 duty configuration bit [11:8]. 097h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw1rl pw1r7 pw1r6 pw1r5 pw1r4 pw1r3 pw1r2 pw1r1 pw1r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit [7:0] pw1r [7:0] = pwm1 duty configuration bit [7:0]. the pwm duty registers length is 1 2 - bit and points to pw 1 r h and pw 1 r l registers. the timer counter is double buffer design. the core bus is 8 - bit, so access 1 2 - bit data needs a latch flag to av oid the transient status affect the 1 2 - bit data mistake occurrence. under write mode, the write pw1r l is the latch control flag. w rite the 12 - bit buffer is to write pw1r h first, and then write pw 1 r l. the 1 2 - bit data is written to 1 2 - bit buffer after execut ing writing pw1r l. ? write pwm 12 - bit duty register sequence is to write pw 1 r h first, and then write pw 1 r l. the pwm duty length is controlled by pwm resolution including 8 - bit, 10 - bit and 12 - bit. if different pwm resolutions, the pwm duty register usable bits are different. ? 8 - bit resolution: pwm duty buffer is pw1r0~pw1r7. pw1r8~pw1r11 are set as 0 . ? 10 - bit resolution: pwm duty buffer is pw1r0~pw1r9. pw1r10~pw1r11 are set as 0 . ? 12 - bit resolution: pwm duty buffer is pw1r0~pw1r11. ? note: pw1r[11:0] written sequence is write pw1r[11:8] first, and then write pw1r[7:0]. end of writing pw1r[7:0] signal means the end of pw1r written.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 114 version 1. 5 9.7 pwm1 operation expla me ? pwm1 configuration : ; reset pwm1 . clr pw1m ; clear pwm1 mode register s . ; set pwm1 clock source, clock rate and resolution . mov a, #0 mmmnll 0b ; mmm is pwm clock rate selection. b0mov pw1m , a ; n is pwm clock source selection. ; ll is pwm resolution selection. ; set the duty of pwm1 . mov a, # value 1 ; set high by te first. b0mov pw1rh , a mov a, # value 2 ; set low byte. b0mov pw1rl , a ; enable pwm1 function. b0b set f pw 1 en ; output pwm signal . b0bset fpw1s ? enable pwm1 synchronous trigger function : (configure pw1rh[5:7] bits for pwm1 synchronous trigger function before enabling pwm1.) ; pwm1 configuration is referred to above example . ; set pwm1 synchronous trigger source and trigger operation . mov a, # n 0 m 000000 b ; n is pwm1 synchronous trigger source selection. or pw1rh , a ; m is pwm1 synchronous trigger operation selection. ; enable pwm1 synchronous trigger function . b0b set f pw 1 gen ; enable pwm1 function. b0b set f pw 1 en ; output pwm signal . b0bset fpw1s
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 115 version 1. 5 ? enable pwm1 inverse outpu t function : (configure pw1nm mode register for pwm1 inverse output function before enabling pwm1.) ; pwm1 configuration is referred to above example . ; reset pw1nm register. clr pw1nm ; select pwm1n pin output signal type. b0b clr f pw 1 nv ; pwm1n pin outputs inverse signal of pwm1. or b0bset f pw 1 nv ; pwm1n pin outputs non - inverse signal of pwm1. ; enable pwm1 inverse output function. b0bset fpw1nen ; enable pwm1 function. b0b set f pw 1 en ; output pwm sign al . b0bset fpw1s ? enable pwm1 dead - band function : (configure pw1nm mode register for pwm1 dead - band function before enabling pwm1.) ; pwm1 configuration is referred to above example . ; pwm1 inverse output function configuration is ref erred to above example . ; set pwm1 dead - band period. mov a , #0 nnn 0000b ; nnn is pw1d[2:0] dead - band period selection. or pw1nm, a ; enable pwm1 dead - band function. b0bset fpw1den ; enable pwm1 inverse output function. b0bset fpw1nen ; enable pwm1 function. b0b set f pw 1 en ; output pwm signal . b0bset fpw1s
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 116 version 1. 5 1 1 1 0 0 0 6 - channel pulse width modulation (pwm2) 10.1 overview the 6 - channel pulse width modulation (pwm) is a high performance design including programma ble high resolution, duty/cycle programmable and high - speed frequency. the pwm resolution is programmable including 8 - bit, 10 - bit and 12 - bit. the pwm cycle is decides by pwm clock source, pwm clock rate selection and pwm resolution. the pwm clock source in cludes fcpu and fhosc. the pwm clock rate includes fhosc/1~fhosc/128 and fcpu/1~fcpu/128. the pwm uses new technology to implement pwm high speed frequency and reduce the ripple effect of output signal. the pwm output pins are shared with gpio pin controll ed by pw2chs register. if the bit of pw2chs register enables, the pwm channel exchanges from gpio to pwm output. when the bit of pw2chs register disables, the pwm channel returns to gpio mode and last status. the 6 - channel easily implements 3 - phase dc moto r control, e.g. bldc motor the pwm main functions are as following. ? high speed - up pwm. ? 8/10/12 - bits programmable resolution with auto reload buffers. ? multi clock source including f h osc, fcpu. ? 6 - channel individual output pins. p w 2 r ( p w m 1 2 - b i t r e l o a d b u f f e r ) p w m d u t y 1 2 - b i t c o m p a r a t i v e b u f f e r p w m 1 2 - b i t u p c o u n t i n g c o u n t e r c o m p a r e r s p w 2 l n [ 1 : 0 ] p w 2 l n [ 1 : 0 ] p w m c o u n t e r o v e r f l o w s i g n a l p w m c o u n t e r o v e r f l o w p w m s i g n a l p w m 2 1 p i n p w 2 e n p w 2 c k s f h o s c f c p u f p w m p w 2 r a t e [ 2 : 0 ] 1 ~ p w 2 c h 1 p w m 2 2 p i n p w 2 c h 2 p w m 2 3 p i n p w 2 c h 3 p w m 2 4 p i n p w 2 c h 4 p w m 2 5 p i n p w 2 c h 5 p w m 2 6 p i n p w 2 c h 6 g p i o g p i o g p i o g p i o g p i o g p i o p w m p h a s e p r o c e s s o r
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 117 version 1. 5 10.2 pwm 2 common operation the pwm is four phases design. one cycle of pwm is combined from four sub - cycle signals. pwm signal keeps original cycle parameter, but the frequency is faster. t he pwm frequency is equal to sub - c ycle ? s frequency. the duty of pwm is placed in each of sub - cycle. the cycle of the above pwm waveform is (t1+t2+t3+t4) / (pwm cycle) . the duty output sequence of the four phases is a special design and more balance. the cycle of pwm is controlled by pw m clock source and pwm clock rate options. pw2cks bit selects pwm clock source (f pwm ) from fhosc and fcpu. pw2rate[2:0] bits selects pwm clock rate from f pwm /1~f pwm /128. so the pwm cycle selection is very flexib le. the pwm reload buffers ( pw2 rh, pw2 rl) d ecide the duty of pwm and through pwm phase processor to allot the duty to each phase. the pwm designs auto - reload function. if modify the pwm duty by program as pwm outputting, the new duty occurs at next cycle and not change immediately. the methods can avoid the transitional duty occurrence . t he pwm resolution includes 8 - bit, 10 - bit and 12 - bit controlled by pw2ln[1:0] bit. pw2ln[1:0]=00 selects 8 - bit pwm. pw2ln[1:0]=01 selects 10 - bit pwm. pw2ln[1:0]=10 selects 12 - bit pwm. the pwm resolution decision de pends on application requirement. the pwm output is controlled by pw2 en bit. pw2en bit controls pwm2 function. when pw2en = 0, the pwm2 is disabled. when pw2en = 1, the pwm2 outputs pwm signal. pw2chs bits control pwm output pin to be gpio or pwm output pin purpose. pw2chs bit 0~6 point to each channel of 6 - channel pwm (pwm21~pwm26). when pw2chs.n = 0, the channel n of pwm2 pins is gpio mode. when pw2chs.n = 1, the channel n of pwm2 pins changes to pwm output pin. pw2chs register is useable as pw2en = 1. the gpio mode of pwm2 output pins can be the idle status of pwm signal. pwm high idle status is gpio output high mode. pwm low idle status is gpio output low mode. pwm high impendence idle status is gpio input mode. sele ct a right pwm ? s idle status is very important for loading control as pwm disable. 0 x 0 0 0 x 0 1 0 x 3 f 8 - b i t p w m c o u n t e r . . . 0 x 4 0 0 x 4 1 0 x 7 f p w m 2 o u t p u t . . . 0 x 8 0 0 x 8 1 0 x b f 0 x 0 0 0 x 0 1 0 x 0 2 . . . e n a b l e p w m 2 . p w m o u t p u t s h i g h s t a t u s . p w m c o u n t e r o v e r f l o w s . p w m e x c h a n g e s t o h i g h s t a t u s . o n e c o m p l e t e c y c l e o f p w m . n e x t c y c l e . . . . 0 x c 0 0 x c 1 . . . 0 x f f p h a s e 1 p h a s e 2 p h a s e 3 p h a s e 4 t 1 t 2 t 3 t 4 0 x 0 0 0 0 x 0 0 1 0 x 0 f f 1 0 - b i t p w m c o u n t e r . . . 0 x 1 0 0 0 x 1 0 1 0 x 1 f f . . . 0 x 2 0 0 0 x 2 0 1 0 x 2 f f 0 x 0 0 0 0 x 0 0 1 0 x 0 0 2 . . . . . . 0 x 3 0 0 0 x 3 0 1 . . . 0 x 3 f f 0 x 0 0 0 0 x 0 0 1 0 x 3 f f 1 2 - b i t p w m c o u n t e r . . . 0 x 4 0 0 0 x 4 0 1 0 x 7 f f . . . 0 x 8 0 0 0 x 8 0 1 0 x b f f 0 x 0 0 0 0 x 0 0 1 0 x 0 0 2 . . . . . . 0 x c 0 0 0 x c 0 1 . . . 0 x f f f p w 2 e n p w 2 c h s . n = 1 ( n = 0 ~ 5 ) i n p u t / o u t p u t p w m 2 c h a n n e l [ m ] o u t p u t p i n ( m = 1 ~ 6 , c h - 1 ~ c h - 6 ) p w m s i g n a l o u t p u t g p i o s t a t u s g p i o s t a t u s p w m s t a r t t o o u t p u t i n p u t / o u t p u t p w m 2 s i g n a l
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 118 version 1. 5 the pwm signal is generated from internal pwm processor and outputs to external pin (pwm21~pwm26) through pwm2 channel selections. the pwm signal of internal source and external pins are the same. the channel selections only switch pwm2 channels and not process the phase of pwm signal. 10.3 pwm2 mode register pw2m register is pwm2 mode control register s to configure pwm operating mode including pwm pre - scaler, clock source, pwm resolution these configurations must be setup completely before enabling pwm2 function. 09 4 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw2 m pw2 en pw2 rate2 pw2 rate1 pw2 rate0 pw2 cks pw2 ln1 pw2 ln0 - read/write r/w r /w r/w r/w r/w r/w r/w - after reset 0 0 0 0 0 0 0 - bit 7 pw2 en: pwm2 control bit. 0 = disable. 1 = enable. bit [6:4] pw2 rate[2:0]: pwm2 clock divide control bit. note: fpwm is pwm2 clock source. 000 = fpwm/128, 001 = fpwm/64, 010 = fpwm/32, 011 = fpwm/16, 100 = fpwm/8, 101 = fpwm/4, 110 = fpwm/2, 111 = fpwm/1. bit 3 pw2 cks: pwm2 clock source select bit. 0 = f h osc. 1 = fcpu. bit [2:1] pw2 ln[1:0]: pwm2 resolution select bit. 00 = 8 - bit. 01 = 10 - bit. 10 = 12 - bit. 11 = reserved. p w 2 c h s . 0 g p i o s t a t u s p w m 2 1 o u t p u t p i n ( c h a n n e l 1 o f p w m 2 ) g p i o s t a t u s p w m 2 s i g n a l p w 2 c h s . 1 g p i o s t a t u s p w m 2 2 o u t p u t p i n ( c h a n n e l 2 o f p w m 2 ) g p i o s t a t u s p w 2 c h s . 2 g p i o s t a t u s p w m 2 3 o u t p u t p i n ( c h a n n e l 3 o f p w m 2 ) g p i o s t a t u s p w 2 c h s . 3 g p i o s t a t u s p w m 2 4 o u t p u t p i n ( c h a n n e l 4 o f p w m 2 ) g p i o s t a t u s p w 2 c h s . 4 g p i o s t a t u s p w m 2 5 o u t p u t p i n ( c h a n n e l 5 o f p w m 2 ) g p i o s t a t u s p w 2 c h s . 5 g p i o s t a t u s p w m 2 6 o u t p u t p i n ( c h a n n e l 6 o f p w m 2 ) g p i o s t a t u s
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 119 version 1. 5 10.4 pwm2 chann el selection registe r pwm2 includes 6 channels selected through pw2chs register. if the related bit of pw2chs register is enabled, the related pin outputs pwm2 signal. if the bit is disabled, the pin returns to last gpio mode. 09 5 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw2 chs - - pw2ch6 pw2ch5 pw2ch4 pw2ch3 pw2ch2 pw2ch1 read/write - - r/w r/w r/w r/w r/w r/w after reset - - 0 0 0 0 0 0 bit 5 pw2 ch6 : pwm2 channel 6 control bit. 0 = disable pwm output . pwm26 pins is p5.7 gpio status. 1 = p wm26 outputs pwm signal and isolate gpio mode. bit 4 pw2 ch5 : pwm2 channel 5 control bit. 0 = disable pwm output . pwm25 pins is p5.6 gpio status. 1 = pwm2 5 outputs pwm signal and isolate gpio mode. bit 3 pw2 ch4 : pwm2 channel 4 control bit. 0 = disa ble pwm output . pwm24 pins is p5.5 gpio status. 1 = pwm2 4 outputs pwm signal and isolate gpio mode. bit 2 pw2 ch3 : pwm2 channel 3 control bit. 0 = disable pwm output . pwm23 pins is p5.3 gpio status. 1 = pwm2 3 outputs pwm signal and isolate gpio mode. bit 1 pw2 ch2 : pwm2 channel 2 control bit. 0 = disable pwm output . pwm22 pins is p5.2 gpio status. 1 = pwm2 2 outputs pwm signal and isolate gpio mode. bit 0 pw2 ch1 : pwm2 channel 1 control bit. 0 = disable pwm output . pwm21 pins is p5.1 gpio status. 1 = pwm2 1 outputs pwm signal and isolate gpio mode. ? note: pw2chs register is workable only when pw2en = 1, or the pwm output pins are gpio mode.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 120 version 1. 5 10.5 pwm2 duty register the duty of pwm2 is decided by pw2 rh, pw2 rl registers. the length of pwm duty reg isters is 12 - bit. the operation is base on pwm counter value and pwm phase processor to generate pwm output signal. the pw2 rh, pw2 rl duty registers build in auto - reload function. i f modify the pwm duty by program as pwm outputting, the new duty occurs at n ext cycle and not change immediately. the methods can avoid the transitional duty occurrence. 09 8 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw2 rh - - - - pw2 r11 pw2 r10 pw2 r9 pw2 r8 read/write - - - - r/w r/w r/w r/w after reset - - - - 0 0 0 0 bit [3:0] pw2 r [11:8] = pwm2 duty configuration bit [11:8]. 09 8 h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 pw2 rl pw2 r7 pw2 r6 pw2 r5 pw2 r4 pw2 r3 pw2 r2 pw2 r1 pw2 r0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit [7:0] pw2 r [7:0] = pwm 2 duty configuration bit [7:0]. the pwm duty registers length is 1 2 - bit and points to pw2r h and pw2r l registers. the timer counter is double buffer design. the core bus is 8 - bit, so access 1 2 - bit data needs a latch flag to avoid the transient status affe ct the 1 2 - bit data mistake occurrence. under write mode, the write pw2r l is the latch control flag. w rite the 12 - bit buffer is to write pw2r h first, and then write pw2r l. the 1 2 - bit data is written to 1 2 - bit buffer after executing writing pw2r l. ? write pw m 12 - bit duty register sequence is to write pw2r h first, and then write pw2r l. the pwm duty length is controlled by pwm resolution including 8 - bit, 10 - bit and 12 - bit. if different pwm resolutions, the pwm duty register usable bits are different. ? 8 - bit resolution: pwm duty buffer is pw2 r0~ pw2 r7. pw2 r8~ pw2 r11 are set as 0 . ? 10 - bit resolution: pwm duty buffer is pw2 r0~ pw2 r9. pw2 r10~ pw2 r11 are set as 0 . ? 12 - bit resolution: pwm duty buffer is pw2 r0~ pw2 r11. ? note: pw2 r[11:0] written sequence is write pw 2 r[11:8] first, and then write pw2 r[7:0]. end of writing pw2 r[7:0] signal means the end of pw2 r written.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 121 version 1. 5 10.6 pwm2 operation expla me ? pwm2 configuration : ; reset pwm2 . clr pw2m ; clear pwm2 mode register s . ; set pwm2 clock source, clock rate and resolution . mov a, #0 mmmnll 0b ; mmm is pwm clock rate selection. b0mov pw2m , a ; n is pwm clock source selection. ; ll is pwm resolution selection. ; set the duty of pwm2 . mov a, # value 1 ; set high byte first. b0mov pw2rh , a mov a, # value 2 ; set low byte. b0mov pw2rl , a ; set pwm ? s idle status. mov a , #11101110b ; pwm21~pwm26 high idle status. or p5, a mov a , #11101110b or p5m, a or mov a , #00010001b ; pwm21~pwm26 low idle status. and p5, a mov a , #11101110b or p5m, a ; enable pwm2 function. b0b set f pw2en ; output pwm signal . b0bset fpw2ch1 ; enable pwm21 output. b0bset fpw2ch2 ; enable pwm22 output. b0bset fpw2ch3 ; enable pwm23 output. b0bset fpw2ch4 ; enable pwm24 output. b0bset fpw2ch5 ; enable pwm25 output. b0bset fpw2ch6 ; enable pwm26 output.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 122 version 1. 5 1 1 1 1 1 1 8 channel analog to digital converter (adc) 11.1 overview the analog to digital converter ( adc ) is sar structure with 8 - input sources and up to 4096 - step resolution to transfer analog signal into 12 - bits digital buffers . the adc builds in 8 - channel input source (ain0~ain7) to measure 8 different analog signal sources controlled by chs[2:0] and gchs bits. the adc resolution can be selected 8 - bit and 12 - bit resolutions through adlen bit. the adc converting rate can be selected by adcks[1:0] bits to decide adc converting time. the adc reference high voltage includes two source s controlled by avrefh bit . one is internal vdd (avrefh=0), and the other one is exte rnal reference voltage input pin from p4.0 pin (avrefh=1). the adc b uild s in p4con register to set pure analog input pin. it is necessary to set p4 as input mode with out pull - up resistor by program. after setup adenb and ads bits, the adc start s to convert analog signal to digital data . when the conversion is complete, the adc circuit will set eoc and adcirq bit s to 1 and the digital data output s in adb and adr register s . if the adcien = 1, the adc interrupt request occurs and executes interrupt service r outine when adcirq = 1 after adc converting. if adc interrupt function is enabled (adcien=1), the system will execute interrupt procedure. the interrupt procedure is system program counter points to interrupt vector (org 8) and executes interrupt service r outine after finishing adc converting. clear adcirq by program is necessary in interrupt procedure. a i n 5 / p 4 . 5 a i n 4 / p 4 . 4 a i n 7 / p 4 . 7 a i n 6 / p 4 . 6 a i n 3 / p 4 . 3 a i n 2 / p 4 . 2 a i n 1 / p 4 . 1 a i n 0 / a v r e f h / p 4 . 0 p 4 c o n c h s [ 2 : 0 ] g c h s i n t e r n a l v d d a d c h i g h r e f e r e n c e v o l t a g e a n a l o g i n p u t a d e n b a d s a d c c l o c k c o u n t e r a d c k s [ 1 : 0 ] a d l e n a d b [ 1 1 : 0 ] e o c a d c i r q 8 / 1 2 a v r e f h s a r a d c a d t a d c o f f s e t c a l i b r a t i o n
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 123 version 1. 5 11.2 ad c mode register ad m is adc mode control register to configure adc configurations including adc start, adc channel selec tion, adc high reference voltage source and adc processing indicator these configurations must be setup completely before starting adc converting. 0b1h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adm adenb ads eoc gchs avrefh chs2 chs1 chs0 read/wr ite r/w r/w r/w r/w r/w r/w r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 adenb: adc control bit. in power saving mode, disable adc to reduce power consumption. 0 = disable adc function. 1 = enable adc function. bit 6 ads: adc start control bit. ads bit is cleared after adc processing automatically. 0 = adc converting stops. 1 = start to execute adc converting. bit 5 eoc: adc status bit. 0 = adc progressing. 1 = end of converting and reset ads bit. bit 4 gchs: adc global channel select bit. 0 = disable ain channel . 1 = enable ain channel . bit 3 avrefh: adc high reference voltage source control bit. 0 = internal vdd. p4.0 is gpio or ain0 pin. 1 = enable external reference voltage from p4.0 . bit [2:0] chs[2:0]: adc input channel select bit. 0 00 = ain0, 001 = ain1, 010 = ain2, 011 = ain3, 100 = ain4, 101 = ain5, 110 = ain6, 111 = ain7 adr register includes adc mode control and adc low - nibble data buffer. adc configurations including adc clock rate and adc resolution. these configurations must be setup completely before starting adc converting. 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr - adcks1 adlen adcks0 adb3 adb2 adb1 adb0 read/write - r/w r/w r/w r r r r after reset - 0 0 0 - - - - bit 6,4 adcks [1:0] : adc?s clock ra te select bit. 00 = fcpu/16 , 01 = fcpu/8 , 10 = fcpu/1, 11 = fcpu/2 bit 5 adlen: adc?s resolution select bits. 0 = 8 - bit . 1 = 12 - bit.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 124 version 1. 5 11.3 adc data buffer registers adc data buffer is 12 - bit length to store adc converter result. the high byte is adb regi ster, and the low - nibble is adr[3:0] bits. the adb register is only 8 - bit register including bit 4~bit11 adc data. to combine adb register and the low - nibble of adr will get full 12 - bit adc data buffer. the adc data buffer is a read - only register and the i nitial status is unknown after system reset. ? adb[11:4]: in 8 - bit adc mode, the adc data is stored in adb register. ? adb[11:0]: in 12 - bit adc mode, the adc data is stored in adb and adr registers. 0b2h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adb adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 read/write r r r r r r r r after reset - - - - - - - - bit[7:0] adb[7:0]: 8 - bit adc data buffer and the high - byte data buffer of 12 - bit adc. 0b3h bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 adr - adcks1 adlen adcks0 adb3 adb2 adb1 adb0 read/write - r/w r/w r/w r r r r after reset - 0 0 0 - - - - bit [3:0] adb [3:0]: 12 - bit low - nibble adc data buffer. the ain input voltage v.s. adb output data ain n adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb 2 adb1 adb0 0/409 6 *vrefh 0 0 0 0 0 0 0 0 0 0 0 0 1/409 6 *vrefh 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4094/409 6 *vrefh 1 1 1 1 1 1 1 1 1 1 1 0 4095/409 6 *vrefh 1 1 1 1 1 1 1 1 1 1 1 1 for different applications, users maybe need more than 8 - bit resolution but less than 12 - bit. to process the adb and adr data can make the job well. first, the adc resolution must be set 12 - bit mode and then to execute adc converter routine. then delete the l sb of adc data and get the new resolution result. the table is as following. adc resolution adb adr adb11 adb10 adb9 adb8 adb7 adb6 adb5 adb4 adb3 adb2 adb1 adb0 8 - bit o o o o o o o o x x x x 9 - bit o o o o o o o o o x x x 10 - bit o o o o o o o o o o x x 11 - bit o o o o o o o o o o o x 12 - bit o o o o o o o o o o o o o = selected, x = useless ? note: the initial status of adc data buffer including adb register and adr low - nibble after the system reset is unknown .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 125 version 1. 5 11.4 adc operation descri ption and notic 11.4.1 adc signal format adc sampling voltage range is limited by high/low reference voltage. the adc low reference voltage is vss and not changeable . the adc high reference voltage includes internal vdd and external reference voltage source from p4.0/avre fh pin controlled by avrefh bit. if avrefh=0, adc reference voltage is from internal vdd (mcu power voltage). if avrefh=1, adc reference voltage is from external voltage source (p4.0/avrefh). adc reference voltage range limitation is ( adc high reference v oltage C low reference voltage) R . adc low reference voltage is vss = 0v. so adc high reference voltage range is 2v~vdd . the range is adc external high reference voltage range. ? adc internal low reference voltage = 0v. ? adc internal high reference vol tage = vdd. (avrefh=0) ? adc external high reference voltage = 2v~vdd. (avrefh=1) adc sampled input signal voltage must be from adc low reference voltage to adc high reference. if the adc input signal voltage is over the range, the adc converting result is error (full scale or zero). ? adc low reference voltage Q Q 11.4.2 adc convert ing time the adc converting time is from ads=1 (start to adc convert) to eoc=1 (end of adc convert). the converting time duration is depend on adc resolution and adc clock rate. 12 - bit ad c ? s convertin g ti me is 1/(adc clock /4)*16 sec , and the 8 - bit adc converting time is 1/(adc clock /4)*1 2 sec. adc clock source is fcpu and includes fcpu/1, fcpu/2, fcpu/8 and fcpu/16 controlled by adcks[1:0] bits. the adc converting time affects adc perfo rmance. if input high rate analog signal, it is necessary to select a high adc converting rate. if the adc converting time is slower than analog signal variation rate, the adc result would be error. so to select a correct adc clock rate and adc resolution to decide a right adc converting rate is very important. 12 - bit adc conversion time = 1/(adc clock rate /4)*16 sec adlen adcks1 , adcks0 adc clock rate fcpu=4mhz fcpu=16mhz adc converting time adc converting rate adc converting time adc convertin g rate 1 ( 12 - bit) 0 0 fcpu/ 16 1/(4mhz/ 1 6 /4 )*1 6 = 256 us 3.906khz 1/( 16 mhz/ 1 6 /4 )*1 6 = 64 us 15.625khz 0 1 fcpu/8 1/(4mhz/8 /4 )*1 6 = 128 us 7.813khz 1/( 16 mhz/8 /4 )*1 6 = 32 us 31.25khz 1 0 fcpu 1/ ( 4mhz /4) *1 6 = 16 us 62.5khz 1/ ( 16 mhz /4) *1 6 = 4 us 250khz 1 1 fcpu/2 1/(4mhz/2 /4 )*1 6 = 32 us 31.25khz 1/( 16 mhz/2 /4 )*1 6 = 8 us 125khz 8 - bit adc conversion time = 1/(adc clock rate /4)*12 sec adlen adcks1 , adcks0 adc clock rate fcpu=4mhz fcpu=16mhz adc converting time adc converting rate adc converti ng time adc converting rate 0 ( 8 - bit) 0 0 fcpu/ 16 1/(4mhz/ 1 6 /4 )*12 = 192 us 5.208khz 1/( 16 mhz/ 1 6 /4 )*1 2 = 48 us 20.833khz 0 1 fcpu/8 1/(4mhz/8 /4 )*12 = 96 us 10.416khz 1/( 16 mhz/8 /4 )*1 2 = 24 us 41.667khz 1 0 fcpu 1/ ( 4mhz /4) *12 = 12 us 83.333khz 1/ ( 16 mh z /4) *1 2 = 3 us 333.333khz 1 1 fcpu/2 1/(4mhz/2 /4 )*12 = 24 us 41.667khz 1/( 16 mhz/2 /4 )*1 2 = 6 us 166.667khz
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 126 version 1. 5 11.4.3 adc pin configuration adc input channels are shared with port4. adc channel selection is through adchs[2:0] bit. adchs[2:0] value points to th e adc input channel directly. adchs[2 :0]=000 selects ain0. adchs[2 :0]=00 1 selects ain 1 only one pin of port 4 can be configured as adc input in the same time. the pins of port4 configured as adc input channel must be set input mode, disable internal pull - up and enable p4con first by program. after selecting adc input channel through adchs[2:0], set gchs bit as 1 to enable adc channel function. ? the gpio mode of adc input channels must be set as input mode. ? the internal pull - up resistor of adc input chan nels must be disabled. ? p4con bits of adc input channel must be set . the p4.0/ain0 can be adc external high reference voltage input pin when avrefh=1. in the condition, p4.0 gpio mode must be set as input mode and disable internal pull - up resistor. ? th e gpio mode of adc external high reference voltage input pin must be set as input mode. ? the internal pull - up resistor of adc external high reference voltage input pin must be disabled. adc input pins are shared with digital i/o pins. connect an analog s ignal to coms digital input pin, especially, the analog signal level is about 1/2 vdd will cause extra current leakage. in the power down mode, the above leakage current will be a big problem. unfortunate ly, if users connect more than one analog input sign al to port 4 will encounter above current leakage situation. p4con is port4 c onfiguration register. write 1 into p4con [7:0] will configure related port 4 pin as pure analog input pin to avoid current leakage. 0aeh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 b it 1 bit 0 p4con p4con7 p4con6 p4con5 p4con4 p4con3 p4con2 p4con1 p4con0 read/write w w w w w w w w after reset 0 0 0 0 0 0 0 0 bit[4:0] p4con[7:0]: p4.n configuration control bits. 0 = p4.n can be an analog input (adc input) or digital i/o pins. 1 = p4.n is pure analog input, can ? t be a digital i/o pin. ? note: when port 4 .n is general i/o port not adc channel, p4con .n must set to 0 or the port 4 .n digital i/o signal would be isolated .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 127 version 1. 5 11.4.4 adc operation examlpe ? adc configuration : ; reset ad c . clr adm ; clear tc0m register. ; set adc clock rate and adc resolution . mov a, #0 n m n 00 0 0b ; nn: adcks[1:0] for adc clock rate. b0mov adr , a ; m: adlen for adc reolution. ; set adc high reference voltage source. b0bclr favrefh ; internal vdd. or b0 bset favrefh ; external reference voltage. ; set adc input channel configuration . mov a, # value 1 ; set p4con for adc input channel. b0mov p4con , a mov a, # value 2 ; set adc input channel as input mode. b0mov p4m , a mov a, # value 3 ; disable adc input channel ? s internal pull - up resistor. b0mov p4ur , a ; enable adc. b0b set f adcenb ; execute adc 100us warm - up time delay loop. call 100usdly ; 100us delay loop. ; select adc input channel. m ov a, # value ; set adchs[2:0] for adc input channel selection. or adm, a ; enable adc input channel. b0bset fgchs ; enable adc interrupt function. b0bclr fadcirq ; clear adc interrupt flag. b0bset fadcien ; enable adc interrupt func tion. ; start to execute adc converting . b0bset fads ? note: 1. when adenb is enabled, the system must be delay 100us to be t he adc warm - up time by program, and then set ads to do adc converting. the 100us delay time is necessary after adenb settin g (not ads setting), or the adc converting result would be error. normally, the adenb is set one time when the system under normal run condition, and do the delay time only one time. 2. in power saving situation like power down mode and green mode, and not us ing adc function, to disable adc by program is necessary to reduce power consumption.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 128 version 1. 5 ? adc converting operation : ; adc interrupt disable mode . @@: b0bts1 feoc ; check adc processing flag. jmp @b ; eoc=0: adc is processing. b0mov a, adb ; eoc =1: end of adc processing . process adc result. b0mov buf1,a mov a, #00001111b and a, adr b0mov buf2,a ; end of processing adc result. clr feoc ; clear adc processing flag for next adc converting. ; adc interrupt enable mode . org 8 ; interrupt vector. int_sr: ; interrupt service routine. push b0bts1 fadcirq ; check adc interrupt flag. jmp exit_int ; adcirq =0: not adc interrupt request . b0mov a, adb ; adcirq=1: end of adc processing . process adc result. b0mov buf1,a mov a, #00001111b and a, adr b0mov buf2,a ? note: ads i s cleared when the end of adc converting automatically. eoc bit indicates adc processing status immediately and is cleared when ads = 1. users needn t to clear ads b it by program.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 129 version 1. 5 11.5 adc application circ uit the analog sig nal is inputted to adc input pin ainn/p4.n . the adc input signal must be through a 0.1uf capacitor a . the 0.1uf capacitor is set between adc input pin and vss pin, and must be on the side of the adc input pin as possible. don ? t connect the capacitor ? s ground pin to ground plain directly, and must be through vss pin. the capacitor can reduce the power noise effective coupled with the analog signal. if the adc high reference voltage is from external voltage source, the external high reference is connect ed to avrefh pin (p4.0). the external high reference source must be through a 47uf c capacitor first, and then 0.1uf capacitor b . these capacitors are set between avrefh pin and vss pin, and must be on the side of the avrefh pin as possible. don ? t conn ect the capacitor ? s ground pin to ground plain directly, and must be through vss pin. v c c g n d 0 . 1 u f a n a l o g s i g n a l i n p u t 4 7 u f 0 . 1 u f e x t e r n a l h i g h r e f e r e n c e v o l t a g e m a i n p o w e r t r u n k a i n n / p 4 . n v s s a v r e f h m c u a b c
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 130 version 1. 5 1 1 1 2 2 2 rail to rail analog comparaotr 12.1 overview the micro - controller builds in 3 sets comparators. the comparators are rail - to - r a il structure. t h at means the input/output voltage is real from vdd~vss. when the positive input voltage is greater than the negative input voltage, the comparator output is high. when the positive input voltage is smaller than the negative input voltage, the comparator output is low. the cmnout and cmnirq bits indicate the comparator result. the cmnout shows the comparator result immediately, but the cmnirq only indicates the even of the comparator result. the even condition is controlled by register and includes risi ng edge (cmnout changes from low to high), falling edge (cmnout changes from high to low) and bi - direction (any cmnout transition occurrence). the cmnirq = 1 condition makes the comparator interrupt service executed when cmnien (comparator interrupt contro l bit) set. the comparator builds in internal reference to replace comparator external positive input source and controlled by cmnref bits. the internal reference voltage is 1/2*vdd. when cmnref = 0, the comparator positive is from external voltage source and cmnp pin. when cmnref = 1, the comparator positive is from internal 1/2*vdd and cmnp pin is gpio function. ? note : cmnout is comparator raw output without latch. it varies depend on the comparator process result. but the cmnirq is latch comparator ou tput result. it must be cleared by program. g p i o / c m n p p i n g p i o g p i o / c m n n p i n g p i o / c m n o p i n + _ v d d v s s ? * v d d c m n r e f g p i o g p i o c m n o e n c m n g 1 , c m n g 0 c m n o u t c m n i r q c m n e n o p n e n v i n + v i n -
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 131 version 1. 5 the c omparator pins are shared with gpio controlled by cmnen bit. when cmnen=1, cmnn pin is enabled connected to comparator negative terminal. cmnoen controls comparator output connected to gpio or not. whe n cmnoen=1, comparator output terminal is connected to gpio pins and isolate gpio function. cmnref controls comparator positive source from internal 1/2*vdd voltage or external input. when cmnref=1, comparator positive voltage is from internal 1/2*vdd volt age, and enable gpio function of cmnp pin. comparator pins selection table is as following. because the pins of comparator and op are the same, comparator control signal and op amp control signal needs some condition to avoi d comparator and op amp enabled at the same time. cmnen and opnen are the same (00 or 11), the pins are gpio mode and disable comparator and op. cmnen=1 and opnen=0, enable comparator and disable op amp. opnen=1 and cmnen=0, enable op amp and disable compa rator. comparator no. cm nen opnen comparator negative pin comparator positive pin comparator output pin cmnref=0 cmnref=1 cmnoen=0 cmnoen=1 cmp0 cm0en=0 op0en=0 all pins are gpio mode. comparator and op amp are disabled. op0en=1 op amp 0 enable . cm0en=1 op0en=0 cm0n cm0p p1. 7 gpio p 5.0 gpio cm0o op0en=1 all pins are gpio mode. comparator and op amp are disabled. cmp1 cm1en=0 op1en=0 all pins are gpio mode. comparator and op amp are disabled. op1en=1 op amp 1 enable. cm1en=1 op1en= 0 cm1n cm1p p 1.4 gpio p1.5 gpio cm1o op1en=1 all pins are gpio mode. comparator and op amp are disabled. cmp2 cm2en=0 op2en=0 all pins are gpio mode. comparator and op amp are disabled. op2en=1 op amp 2 enable. cm2en=1 op2en=0 cm2n cm2p p 1.1 gpi o p 1.2 gpio cm2o op2en=1 all pins are gpio mode. comparator and op amp are disabled. ? note : the comparator enable condition is fixed cmnen=1 and opnen=0, or the comparator pins are gpio mode and comparators are disabled. c m n n c m n o g p i o = c m n p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m n n c m n o c m n p = g p i o + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c i n t e r n a l r e f e r e n c e v o l t a g e c m n n c m n o = g p i o c m n p + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c c m n n c m n o = g p i o c m n p = g p i o + - c o m p a r a t o r c o m p a r a t o r i n t e r n a l l o g i c i n t e r n a l r e f e r e n c e v o l t a g e c m n e n = 1 , c m n o e n = 1 , c m n r e f = 0 c m n e n = 1 , c m n o e n = 1 , c m n r e f = 1 c m n e n = 1 , c m n o e n = 0 , c m n r e f = 0 c m n e n = 1 , c m n o e n = 0 , c m n r e f = 1
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 132 version 1. 5 12.2 comparator mode regist er 09ch bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmp0m cm0en cm0ien cm0irq cm0oen cm0ref cm0out cm0g1 cm0g0 read/write r/w r/w r/w r/w r/w r r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 cm0en: comparator 0 control bit. 0 = disable. p1.6, p1.7, p5 .0 are gpio mode. 1 = enable. p1.6 is cm0n pin. bit 6 cm0ien: comparator 0 interrupt function control bit. 0 = disable. 1 = enable. bit 5 cm0irq: comparator 0 interrupt request bit. 0 = non comparator interrupt request. 1 = announce comparator interr upt request. bit 4 cm0oen: comparator 0 output pin control bit. 0 = disable. cm0o is p5.0 gpio mode. 1 = enable. cm0o is comparator output pin and isolate p5.0 gpio function. bit 3 cm0ref: comparator 0 internal reference voltage source control bit. 0 = disable. cm0p input pin is comparator positive input pin, and isolate p1.7 gpio function. 1 = enable. cm0p pin is p1.7 gpio mode. bit 2 cm0out: comparator 0 output flag bit. 0 = cm0p voltage or comparator internal reference voltage is less than cm0n voltage. 1 = cm0p voltage or comparator internal reference voltage is larger than cm0n voltage. bit [1:0] cm0g[1:0]: comparator interrupt trigger direction control bit. 00 = reserved. 01 = rising edge trigger. cm0p > cm0n or comparator internal refe rence voltage. 10 = falling edge trigger. cm0p < cm0n or comparator internal reference voltage. 11 = both rising and falling edge trigger (level change trigger).
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 133 version 1. 5 09dh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmp1m cm1en cm1ien cm1irq cm1oen cm1 ref cm1out cm1g1 cm1g0 read/write r/w r/w r/w r/w r/w r r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 cm1en: comparator 1 control bit. 0 = disable. p1.3, p1.4, p1.5 are gpio mode. 1 = enable. p1.3 is cm1n pin. bit 6 cm1ien: comparator 1 interrupt functi on control bit. 0 = disable. 1 = enable. bit 5 cm1irq: comparator 1 interrupt request bit. 0 = non comparator interrupt request. 1 = announce comparator interrupt request. bit 4 cm1oen: comparator 1 output pin control bit. 0 = disable. cm1o is p1.5 gpio mode. 1 = enable. cm1o is comparator output pin and isolate p1.5 gpio function. bit 3 cm1ref: comparator 1 internal reference voltage source control bit. 0 = disable. cm1p input pin is comparator positive input pin, and isolate p1.4 gpio function. 1 = enable. cm1p pin is p1.4 gpio mode. bit 2 cm1out: comparator 1 output flag bit. 0 = cm1p voltage or comparator internal reference voltage is less than cm1n voltage. 1 = cm1p voltage or comparator internal reference voltage is larger than cm1n volta ge. bit [1:0] cm1g[1:0]: comparator interrupt trigger direction control bit. 00 = reserved. 01 = rising edge trigger. cm1p > cm1n or comparator internal reference voltage. 10 = falling edge trigger. cm1p < cm1n or comparator internal reference voltag e. 11 = both rising and falling edge trigger (level change trigger).
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 134 version 1. 5 09eh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cmp2m cm2en cm2ien cm2irq cm2oen cm2ref cm2out cm2g1 cm2g0 read/write r/w r/w r/w r/w r/w r r/w r/w after reset 0 0 0 0 0 0 0 0 bit 7 cm2en: comparator 2 control bit. 0 = disable. p1.0, p1.1, p1.2 are gpio mode. 1 = enable. p1.0 is cm2n pin. bit 6 cm2ien: comparator 2 interrupt function control bit. 0 = disable. 1 = enable. bit 5 cm2irq: comparator 2 interrupt request bit. 0 = non comparator interrupt request. 1 = announce comparator interrupt request. bit 4 cm2oen: comparator 2 output pin control bit. 0 = disable. cm2o is p1.2 gpio mode. 1 = enable. cm2o is comparator output pin and isolate p1.2 gpio function. bit 3 cm2ref: comparator 2 internal reference voltage source control bit. 0 = disable. cm2p input pin is comparator positive input pin, and isolate p1.1 gpio function. 1 = enable. cm2p pin is p1.1 gpio mode. bit 2 cm2out: comparator 2 output flag bit. 0 = cm 2p voltage or comparator internal reference voltage is less than cm2n voltage. 1 = cm2p voltage or comparator internal reference voltage is larger than cm2n voltage. bit [1:0] cm2g[1:0]: comparator interrupt trigger direction control bit. 00 = reserved . 01 = rising edge trigger. cm2p > cm2n or comparator internal reference voltage. 10 = falling edge trigger. cm2p < cm2n or comparator internal reference voltage. 11 = both rising and falling edge trigger (level change trigger).
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 135 version 1. 5 12.3 comparator applic ation notice the comparator is to compares the positive voltage and negative voltage to output result. the positive and negative sources are analog signal. in hardware application circuit, the comparator input pins must be connected a 0.1uf comparator to r educe power noise and make the input signal more stable. the application circuit is as following . ? example: use comparator 0 to measure the external analog signal . when the analog signal is smaller than 1/2*vdd, to execute i nterrupt service routine. in the case, use comparator interface 1/2*vdd reference to be the comparator positive voltage source. the interrupt trigger condition is comparator output from low to high rising edge. ; the comparator 0 initialize. mov a, # 01001001b ; cm0ref=1, enable comparator internal 1/2*vdd reference b0mov cm p 0m, a ; voltage to be comparator positive source. ; cm0g1, cm0g0=01, set comparator interrupt request ; condition to be rising edge. ; cm0ien=1, enable comparator 0 i nterrupt function. ; cm0irq=0, clear comparator 0 interrupt request flag. b0bset fcm0en ; enable comparator 0. main: ; main loop. m c u c m n n 0 . 1 u f c m n p 0 . 1 u f c m n o c o m p a r a t o r o u t p u t c o m p a r a t o r n e g a t i v e i n p u t c o m p a r a t o r p o s i t i v e i n p u t
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 136 version 1. 5 1 1 1 3 3 3 rail to ra il op amplifer 13.1 overview the micro - controller builds in 3 sets op amp. the comparators are rail - to - r a il structure. t h at means the input/output voltage is real from vdd~vss. the rail - to - rail op amp pins are shared with gpio c ontrolled by opnen bit. when opnen=1, gpio pins switch to op amp and isolate gpio path. op pins selection table is as following. because the pins of comparator and op are the same, comparator control signal and op amp control signal needs some condition t o avoid comparator and op amp enabled at the same time. cmnen and opnen are the same (00 or 11), the pins are gpio mode and disable comparator and op. cmnen=1 and opnen=0, enable comparator and disable op amp. opnen=1 and cmnen=0, enable op amp and disable comparator. op no. opnen cmnen op positive pin op negative pin op output pin op0 op0en=0 cm0en=0 all pins are gpio mode. comparator and op amp are disabled. cm0en=1 comparator 0 enable. op0en=1 cm0en=0 op0p (vin+) op0n (vin - ) op0o (vout) cm0e n=1 all pins are gpio mode. comparator and op amp are disabled. op1 op1en=0 cm1en=0 all pins are gpio mode. comparator and op amp are disabled. cm1en=1 comparator 1 enable. op1en=1 cm1en=0 op1p (vin+) op1n (vin - ) op1o (vout) cm1en=1 all pins are gpio mode. comparator and op amp are disabled. op2 op2en=0 cm2en=0 all pins are gpio mode. comparator and op amp are disabled. cm2en=1 comparator 2 enable. op2en=1 cm2en=0 op2p (vin+) op2n (vin - ) op2o (vout) cm2en=1 all pins are gpio mode. comp arator and op amp are disabled. ? note : the op amp enable condition is fixed opnen=1 and cmnen=0, or the op amp pins are gpio mode and comparators are disabled. o p n e n g p i o / o p n p p i n g p i o + _ v d d v s s g p i o / o p n n p i n g p i o g p i o / o p n o p i n g p i o v o u t v i n + v i n - c m n e n
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 137 version 1. 5 13.2 op amp register 09fh bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 opm - - - - - op2e n op1en op0en read/write - - - - - r/w r/w r/w after reset - - - - - 0 0 0 bit 2 op2en: op amp 2 control bit. 0 = disable. p 1 .0~p 1 .2 are gpio mode or comparator mode. 1 = enable. p 1 .0~p 1 .2 are op amp pins. bit 1 op1en: op amp 1 control bit. 0 = disab le. p1.3~p1.5 are gpio mode or comparator mode. 1 = enable. p1.3~p1.5 are op amp pins. bit 0 op0en: op amp 0 control bit. 0 = disable. p1. 6, p1.7, p 5.0 are gpio mode or comparator mode. 1 = enable. p1. 6, p1.7, p 5.0 are op amp pins.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 138 version 1. 5 1 1 1 4 4 4 instruction table f ield mnemonic description c dc z cycle mov a,m a ? m - - ? 1 m mov m,a m ? a - - - 1 o b0mov a,m a ? m (b an k 0) - - ? 1 v b0mov m,a m (bank 0) ? a - - - 1 e mov a,i a ? i - - - 1 b0mov m,i m ? i, m only supports 0x80~0x87 registers (e.g. pf lag,r,y,z ) - - - 1 xch a,m a ? ? m - - - 1 +n b0xch a,m a ? ? m (bank 0) - - - 1 +n movc r, a ? rom [y,z] - - - 2 adc a,m a ? a + m + c, if occur carry, then c=1, else c=0 ? ? ? 1 a adc m,a m ? a + m + c, if occur carry, then c=1, else c=0 ? ? ? 1 +n r add a,m a ? a + m, if occur carry, then c=1, else c=0 ? ? ? 1 i add m,a m ? a + m, if occur carry, then c=1, else c=0 ? ? ? 1 +n t b0add m,a m (bank 0) ? m (bank 0) + a, if occur carry, then c=1, else c=0 ? ? ? 1 +n h add a,i a ? a + i, if oc cur carry, then c=1, else c=0 ? ? ? 1 m sbc a,m a ? a - m - /c, if occur borrow, then c=0, else c=1 ? ? ? 1 e sbc m,a m ? a - m - /c, if occur borrow, then c=0, else c=1 ? ? ? 1 +n t sub a,m a ? a - m, if occur borrow, then c=0, else c=1 ? ? ? 1 i s ub m,a m ? a - m, if occur borrow, then c=0, else c=1 ? ? ? 1 +n c sub a,i a ? a - i, if occur borrow, then c=0, else c=1 ? ? ? 1 daa to adjust acc?s data format from hex to dec. ? - - 1 mul a,m r, a ? a * m, the lb of product stored in acc and hb stored in r register. zf affected by acc. - - ? 2 and a,m a ? a and m - - ? 1 l and m,a m ? a and m - - ? 1 +n o and a,i a ? a and i - - ? 1 g or a,m a ? a or m - - ? 1 i or m,a m ? a or m - - ? 1 +n c or a,i a ? a or i - - ? 1 xor a,m a ? a xor m - - ? 1 xor m,a m ? a xor m - - ? 1 +n xor a,i a ? a xor i - - ? 1 swap m a (b3~b0, b7~b4) ? m(b7~b4, b3~b0) - - - 1 p swapm m m(b3~b0, b7~b4) ? m(b7~b4, b3~b0) - - - 1 +n r rrc m a ? rrc m ? - - 1 o rrcm m m ? rrc m ? - - 1 +n c rlc m a ? rlc m ? - - 1 e rlcm m m ? rlc m ? - - 1 +n s clr m m ? 0 - - - 1 s bclr m.b m.b ? 0 - - - 1 +n bset m.b m.b ? 1 - - - 1 +n b0bclr m.b m(bank 0).b ? 0 - - - 1 +n b0bset m.b m(bank 0).b ? 1 - - - 1 +n cmprs a,i zf,c ? a - i, if a = i, then skip next instruction ? - ? 1 + s b cmprs a,m zf,c ? a C m, if a = m, then skip next instruction ? - ? 1 + s r incs m a ? m + 1, if a = 0, then skip next instruction - - - 1+ s a incms m m ? m + 1, if m = 0, then skip next instruction - - - 1 +n +s n decs m a ? m - 1, if a = 0, then skip next instruction - - - 1+ s c decms m m ? m - 1, if m = 0, then skip next instruction - - - 1 +n +s h bts0 m.b if m.b = 0, then skip next instruction - - - 1 + s bts1 m.b if m.b = 1, then skip next instruction - - - 1 + s b0bts0 m.b if m(bank 0).b = 0, then skip next instruction - - - 1 + s b0bts1 m.b if m(bank 0).b = 1, then skip next instruction - - - 1 + s jmp d pc15/14 ? rompages1/0, pc13~pc0 ? d - - - 2 call d stack ? pc15~pc0, pc15/14 ? rompa ges1/0, pc13~pc0 ? d - - - 2 m ret pc ? stack - - - 2 i reti pc ? stack, and to enable global interrupt - - - 2 s push to push acc and pflag (except nt0, npd bit) into buffers . - - - 1 c pop to pop acc and pflag (except nt0, npd bit) from buffe rs . ? ? ? 1 nop no operation - - - 1 note: 1. m is system register or ram. if m is system registers then n = 0, otherwise n = 1. 2. if branch condition is true then s = 1, otherwise s = 0.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 139 version 1. 5 1 1 1 5 5 5 electrical characteristic 15.1 absolute maximum rating supply voltage (vdd) . - 0.3v ~ 6.0v input in voltage (vin) . vss C 0.2v ~ vdd + 0.2v operating ambient temperature (topr) sn8p27 35 p, sn8p27 35f, sn8p2734 k, sn8p2734s, SN8P2733k, SN8P2733s, sn8p2732p, sn8p2732s . - 2 0 ? c ~ + 85 ? c sn8p 2735pd , sn8p 2735fd, sn8p2734kd, sn8p2734sd, SN8P2733kd, SN8P2733sd, sn8p2732pd, sn8p2732sd . C 4 0 ? c ~ + 8 5 ? c storage ambient temperature (tstor) . C 4 0 ? c ~ + 125 ? c 15.2 e lectrical characteri stic ? dc characteristic (all of voltages refer to vss, vdd = 5.0v, f osc = 4 mhz, fcpu=1mhz, ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. unit operating v oltage vdd normal mode, vpp = vdd , 25 ? 1.8 - 5.5 v normal mode, vpp = vdd , - 40 ? ? 2.4 - 5.5 v ram data retention voltage vdr 1.5 - - v * vdd rise rate vpor vdd rise rate to ensure internal power - on reset 0.05 - - v/ms input low volta ge vil1 all input ports vss - 0.3vdd v vil2 reset pin vss - 0.2vdd v input high voltage vih1 all input ports 0.7vdd - vdd v vih2 reset pin 0. 9 vdd - vdd v reset pin leakage current ilekg vin = vdd - - 2 ua i/o port input leakage current ilekg pull - up resistor disable, vin = vdd - - 2 ua i/o port pull - up resistor rup vin = vss , vdd = 3v 100 200 300 k ? vin = vss , vdd = 5v 50 100 150 i/o output source current ioh vop = vdd C 0.5v 8 - - ma sink current iol vop = vss + 0.5v 8 - - * intn trigger p ulse width tint0 int0 interrupt request pulse width 2/fcpu - - cycle supply current (disable adc, op - amp, comparator) idd1 run mode (n o loading ) vdd= 3 v , fcpu = 8mhz - 5 - ma vdd= 5 v , fcpu = 8mhz - 7 - ma vdd= 3 v , fcpu = 4mhz - 2 - ma vdd= 5 v , fcpu = 4mhz - 4 - ma vdd= 3 v , fcpu = 1mhz - 1.5 - ma vdd= 5 v , fcpu = 1mhz - 3 - ma vdd= 3 v , fcpu = 32khz - 20 - u a vdd= 5 v , fcpu = 32khz - 45 - u a idd2 slow m ode ( internal low rc, stop high clock ) vdd= 3 v , ilrc=16khz - 3.5 - u a vdd = 5 v , ilrc=32khz - 10 - ua idd3 sleep mode vdd= 5v/3v - 1 2 ua idd4 green mode (n o loading , watchdog disable) vdd= 5v , ihrc=8mhz - 0.35 - ma vdd= 3 v , ihrc=8mhz - 0.55 - ma vdd= 3 v , ext. 32khz x ? tal - 6 - ua vdd= 5 v , ext. 32khz x ? tal - 18 - ua vdd= 3 v , ilrc=16khz - 3 - ua vdd= 5 v , ilrc=32khz - 5.5 - ua internal high oscillator freq. fihrc internal hihg rc (ihrc) 25 ? vdd= 2.2v~ 5. 5v fcpu=fhosc/2~fhosc/16 15.68 16 16.32 mhz - 40 ? ? vdd= 2.4v~ 5. 5v fcpu=fhosc/2~fhosc/16 15.2 1 6 16.8 mhz lvd voltage vdet0 low voltage reset level. 25 ? 1.7 1.8 1.9 v low voltage reset level. - 40 ? ? 1.6 1.8 2. 1 v vdet1 low voltage reset /indicator level. 25 ? 2. 3 2. 4 2.5 v low voltage reset /indicator level. - 40 ? ? 2.2 2. 4 2.7 v vdet2 low voltage reset /indicator level. 25 ? 3.5 3. 6 3.7 v low voltage reset /indicator level. - 40 ? ? 3.3 3. 6 3.9 v * these parameters are for design reference, not tested.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 140 version 1. 5 ? adc characteristic (all of voltages refer to vss, vdd = 5.0v, f os c = 4 mhz, fcpu=1mhz, ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. unit ain0 ~ ain7 input voltage vani vdd = 5.0v 0 - avrefh v adc reference voltage vref 2 - - v *adc enable time tast ready to start convert after set adenb = 1 100 - - us *adc current consumption i adc vdd=5.0v - 0.6 - ma vdd=3.0v - 0.4 - ma adc clock frequency f adclk vdd=5.0v - - 8m hz vdd=3.0v - - 5m hz adc conversion cycle time f adcyl vdd=2.4v~5.5v 64 - - 1/f adcl k adc sampling r ate (set fads=1 frequency) f adsmp vdd=5.0v - - 125 k/sec vdd=3.0v - - 80 k/sec differential nonlinearity dnl vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 1 - - lsb integral nonlinearity inl vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 2 - - lsb no missing code nmc vdd=5.0v , avrefh=3.2v, f adsmp =7.8k 10 11 12 bits adc offset voltage v adc offset non - trimmed - 10 0 +10 mv trimmed - 2 0 +2 mv * these parameters are for design reference, not tested. ? op amp characteristic (all of voltages refer to vss, vdd = 5.0v, f osc = 4 mhz, fcpu=1mhz, ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. unit *supply current i op iout=0 , vdd= 3v - 1 3 0 - ua iout=0 , vdd= 5v - 150 - ua * quiescent current iq op - amp disable. - - 1 ua common mode input voltage range vcmr vdd=5.0v vss - 0.3 - vdd+0.3 v input offset voltage vos vcm=vss - 3 - +3 mv power supply rejection ratio psrr vcm=vss 50 - 70 db common mode rejection ratio cmrr vcm= - 0.3v~2.5v. vdd=5v. 50 - 80 db open - loop gain (large sign al) aol vout=0.2v~vdd - 0.2v. vcm=vss. 90 110 - db maximum output voltage swing vol, voh 0.5v output overdrive. vss+15 vdd - 15 v output short current isc unit gain buffer. vo = vss~vdd, vdd=3v - 15 - +15 ma unit gain buffer. vo = vss~vdd, vdd= 5 v - 40 - +4 0 ma output slew rate tosr vo = vss to vdd, vdd to vss. 3 - 5 us ? comparator characteristic (all of voltages refer to vss, vdd = 5.0v, f osc = 4 mhz, fcpu=1mhz, ambient temperature is 25 ? c unless otherwise n ote.) parameter sym. description min. typ. max. un it *supply current i cm iout=0 , vdd= 3v - 1 3 0 - ua iout=0 , vdd= 5v - 150 - ua * quiescent current iq op - amp disable. - - 1 ua input offset voltage vos vcm=vss - 3 + 3 mv common mode input voltage range vcmr vdd=5.0v vss - 0.3 vdd+0.3 v output slew rat e tosr vo = vss to vdd, vdd to vss. 1 - 2 us * these parameters are for design reference, not tested.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 141 version 1. 5 15.3 characteristic graph s the graphs in this section are for design guidance, not tested or guaranteed. in some graphs, the data presented are outside s pecified operating range. this is for information only and devices are guaranteed to operate properly only within the specified range. 14.00 14.50 15.00 15.50 16.00 16.50 17.00 17.50 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v freq. (mhz) vdd (v) internal high rc oscillator (mhz) ( fcpu = ihrc/2~ihrc/16 ) 0 70 25 - 40 85 14.60 14.80 15.00 15.20 15.40 15.60 15.80 16.00 16.20 16.40 16.60 16.80 - 40 0 25 70 85 freq. (mhz) tempeture ( ) internal high rc oscillator (mhz) (fcpu=ihrc/2~ihrc/16) vdd=5v vdd=3v 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 45.00 50.00 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v freq. (khz) vdd (v) internal low rc oscillator (khz) 0 70 25 - 40 85 0.00 5.00 10.00 15.00 20.00 25.00 30.00 35.00 40.00 - 40 0 25 70 85 freq. (khz) tempeture ( ) internal low rc oscillator (khz) vdd=5v vdd=3v 0.00 5.00 10.00 15.00 20.00 25.00 2.5v 3.0v 3.5v 4.0v 4.5v 5.0v 5.5v 6.0v mhz vdd (v) external rc oscillator (25 ) 10k 100p 3.3k 100p 3.3k 20p 5.1k 2 0p 5.1k 100p 0.00 1.00 2.00 3.00 4.00 5.00 6.00 1mhz 2mhz 4mhz 8mhz 16mhz vdd (v) fcpu system minmum operating voltage vmin vmax = 5.5v
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 142 version 1. 5 1 1 1 6 6 6 development tool sonix provides ice (in circuit emulation), ide ( integrated development environme nt) and ev - kit for sn8p 2735 development. ice and ev - kit are external hardware devices, and ide is a friendly user interface for firmware development and emulation. these development tools? version is as following. ? ice: sn8ice2k plus ii. (please install 16 mhz crystal in ice to implement ihrc emulation.). ? ice emulation speed maximum: 8 mips @ 5v (e.g. 16mhz crystal, fcpu = fosc/2). ? ev - kit: sn8p 2735 _ev kit rev. d . ? ide: sonix ide m2ide_v 120 . ? writer: mpiii writer. ? writer transition board: sn8p2 735/ sn8p273 4/ s n8p273 3/ sn8p273 2 16.1 sn8p 2735 ev - kit sonix provides sn8p2735 mcu which includes multi - pwm, adc, comparator and op analog functions. these functions aren?t built in sn8ice2k plus. to emulate the functions must be through sn8p2735 real chip. the real chip p rovi d es a n ev - kit to achieve multi - pwm and the analog functions emulations. for sn8p2735 ice emulation, the ev - kit includes op / comparator / pwm / adc / lvd2.4v / 3.6v and switch circuits. sn8p 2735 ev - kit pcb outline: ? con1 : connect to sn8ice 2k plus con1 (includes gpio, ev - kit control signal, and the others). ? con2 : connect to sn8ice 2k plus jp3 (ev - kit communication bus with ice, control signal, and the others). ? s1 : lvd24v / lvd36v control switch. to emulate lvd2.4v flag / reset function and lvd3.6v / fla g function switch no. on off lvd24 lvd 2.4v active lvd 2.4v inactive lvd36 lvd 3.6v active lvd 3.6v inactive ? jp 8 : gpio connector. ? u 1 : sn8p 2735 ev - chip for analog functions emulation. ? u 2 : sn8p 2735 dip form connector for connecting to user?s target boar d. ? u 21 : sn8p 2735 lqfp form connector for connecting to user?s target board. ? jp15 : using adc function before, sn8ice 2k plus avrefh/vdd jumper pin must be removed. if adc external reference voltage function enable, jp15 (avrefh) or p40o is external referenc e voltage input. ? c17~c19,c22~c26 : connect 0.1uf capacitors to ain0~ain7 input which are adc channel 0~7 bypass capacitors.
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 143 version 1. 5 ? c27 : connect 0.1uf capacitors to avrefh input which are adc reference voltage bypass capacitors. ? s2 : reset key. if ev - kit active fa il, press s2 to reset ev - kit real chip (u1). ? jp16 ~ jp18 : observe cmp0~cmp2 / op - amp0~op - amp2 input/output voltage. ? c28~c36 : comparator or op - amp bypass capacitors sn8p 2735 ev - kit schematic: 16.2 ice and ev - kit application noti c 1. sn8ice2k plus power switch must be turned off before you connect the sn8p2735 ev - kit to sn8ice2k plus. 2. connect ev - kit?s con1/con2 to ice?s con1/jp3. 3. sn8ice2k plus?s avrefh/vdd jumper pin must be removed. 4. turn on sn8ice2k plus power switch after user had finished step 1~3. 5. it is nec essary to connect 16mhz crystal in ice for ihrc_8m mode emulation. 6. when adc function enable. the adm?s bit 3 (favrefh) is set as high. p40o or jp15 (avrefh) will be external reference voltage input pin. 7. when adc function enable. the adm?s bit 3 (favrefh) is set as low. p40o will be analog signal input pin. jp15 (avrefh) do not connect power device. 8. observe adc internal or external reference voltage is jp15(avrefh) . 9. the op - amp0 of sn8p2735 application circuit is as the below figure (op - amp connect). c o n n e c t t o j p 8 ' s p 1 6 o p i n . c o n n e c t t o p 5 0 o ( j p 8 ) p i n . c o n n e c t t o p 1 7 o ( j p 8 ) p i n .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 144 version 1. 5 10. when sn8p2735?s op - amp0 function enable as the above figure. p50o (jp8) is op - amp0?s output. p17o (jp8) is op - amp0?s non - inverse. p16o (jp8) is op - amp0?s inverse. 11. if user want to measure op - amp0 v+ / v - / vo voltage as the above fig ure, the real op - amp0?s inverse voltage is cm0n (jp16). the real op - amp0?s non - inverse voltage is cm0p (jp16). the real op - amp0?s output voltage is cm0o (jp16). 12. if user use op - amp1 to replace op - amp0 as the above figure circuit, p15o (jp8) is op - amp1?s out put. p14o (jp8) is op - amp1?s non - inverse. p13o (jp8) is op - amp1?s inverse. 13. if user want to measure op - amp1 v+ / v - / vo voltage as the above figure, the real op - amp1?s inverse voltage is cm1n (jp17). the real op - amp1?s non - inverse voltage is cm1p (jp17). t he real op - amp1?s output voltage is cm1o (jp17). 14. if user use op - amp2 to replace op - amp0 as the above figure circuit, p12o (jp8) is op - amp2?s output. p11o (jp8) is op - amp2?s non - inverse. p10o (jp8) is op - amp2?s inverse. 15. if user want to measure op - amp2 v+ / v - / vo voltage as the above figure, the real op - amp2?s inverse voltage is cm2n (jp18). the real op - amp2?s non - inverse voltage is cm2p (jp18). the real op - amp2?s output voltage is cm2o (jp18). 16. why op - amp connecting is different with measurement, because op - amp series connection with analog switch internal resistor (ron).
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 145 version 1. 5 1 1 1 7 7 7 otp programming pin 17.1 writer transition bo ard socket pin assignment jp3 (mapping to 48 - pin text tool) writer jp1/jp2 dip 1 1 48 dip48 vdd 1 2 vss dip 2 2 47 dip47 clk/pgclk 3 4 ce dip 3 3 46 dip46 pgm/otpclk 5 6 oe/shiftdat dip 4 4 45 dip45 d1 7 8 d0 dip 5 5 44 dip44 d3 9 10 d2 dip 6 6 43 dip43 d5 11 12 d4 dip 7 7 42 dip42 d7 13 14 d6 dip 8 8 41 dip41 vdd 15 16 vpp dip 9 9 40 dip40 hls 17 18 rst dip10 10 39 dip39 - 19 20 alsb/pdb dip11 11 38 dip38 dip12 12 37 dip37 jp1 for writer transition board dip13 13 36 dip36 jp2 for dice and >48 pin package dip14 14 35 dip35 dip15 15 34 dip34 dip16 16 33 dip33 dip17 17 32 dip32 dip18 18 31 dip31 dip19 19 30 dip30 dip20 20 29 dip29 dip21 21 28 dip28 dip22 22 27 dip27 dip23 23 26 dip26 dip24 24 25 dip25 p i n 1 p i n 4 8 p i n 2 4 p i n 2 5 4 8 4 0 2 8 1 8 1 4 48 40 28 18 14
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 146 version 1. 5 17.2 programm ing pin mapping: programming pin information of sn8p2735 series chip name sn8p2735p(p - dip) sn8p2735f(lqfp) writer connector ic and jp3 48 - pin text tool pin assignment jp1/jp2 pin number jp1/jp2 pin name ic pin n umber ic pin name jp3 pin number ic pin n u mber ic pin name jp3 pin number 1 vdd 32 vdd 40 28 vdd 36 2 gnd 1 vss 9 29 vss 37 3 clk 24 p 4 . 0 32 20 p 4 . 0 28 4 ce - - - - - - 5 pgm 28 p 4.4 36 24 p 4.4 32 6 oe 25 p 4.1 33 21 p 4.1 29 7 d1 - - - - - - 8 d0 - - - - - - 9 d3 - - - - - - 10 d2 - - - - - - 11 d5 - - - - - - 12 d4 - - - - - - 13 d7 - - - - - - 14 d6 - - - - - - 15 vdd - - - - - - 16 vpp 4 rst 12 32 rst 40 17 hls - - - - - - 18 rst - - - - - - 19 - - - - - - - 20 alsb/pdb 3 p 0.4 11 31 p 0.4 39 programming pin information of sn8 p2735 series chip name sn8p2734k/s(skdip/sop) SN8P2733k/s(skdip/sop) writer connector ic and jp3 48 - pin text tool pin assignment jp1/jp2 pin number jp1/jp2 pin name ic pin n umber ic pin name jp3 pin number ic pin n umber ic pin name jp3 pin number 1 vdd 28 vdd 38 24 vdd 36 2 gnd 1 vss 11 1 vss 13 3 clk 20 p 4 . 0 30 16 p 4 . 0 28 4 ce - - - - - - 5 pgm 24 p 4.4 34 20 p 4.4 32 6 oe 21 p 4.1 31 17 p 4.1 29 7 d1 - - - - - - 8 d0 - - - - - - 9 d3 - - - - - - 10 d2 - - - - - - 11 d5 - - - - - - 12 d4 - - - - - - 13 d7 - - - - - - 14 d6 - - - - - - 15 vdd - - - - - - 16 vpp 4 rst 14 4 rst 16 17 hls - - - - - - 18 rst - - - - - - 19 - - - - - - - 20 alsb/pdb 3 p 0.4 13 3 p 0.4 15
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 147 version 1. 5 programming pin information of sn8p2735 series chip name sn8p2732p/s(p - di p/sop) writer connector ic and jp3 48 - pin text tool pin assignment jp1/jp2 pin number jp1/jp2 pin name ic pin n umber ic pin name jp3 pin number ic pin n umber ic pin name jp3 pin number 1 vdd 20 vdd 34 2 gnd 1 vss 15 3 clk 13 p 4 . 0 27 4 ce - - - 5 pgm 17 p 4.4 31 6 oe 14 p 4.1 28 7 d1 - - - 8 d0 - - - 9 d3 - - - 10 d2 - - - 11 d5 - - - 12 d4 - - - 13 d7 - - - 14 d6 - - - 15 vdd - - - 16 vpp 4 rst 18 17 hls - - - 18 rst - - - 19 - - - - 20 alsb/pdb 3 p 0.4 17
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 148 version 1. 5 1 1 1 8 8 8 marking definition 18.1 introduction there are many different types in sonix 8 - bit mcu production line. this note listed the production definition of all 8 - bit mcu for order or obtain information. this definition is only for bl ank otp mcu. 18.2 marking indetificati on system t i t l e s o n i x 8 - b i t m c u p r o d u c t i o n r o m t y p e m a t e r i a l b = p b - f r e e p a c k a g e g = g r e e n p a c k a g e t e m p e r a t u r e r a n g e - = - 2 0 ~ 8 5 s h i p p i n g p a c k a g e w = w a f e r , h = d i c e p = p - d i p , s = s o p x = s s o p , f = l q f p k = s k - d i p d e v i c e s n 8 x p a r t n o . x x x d = - 4 0 ~ 8 5
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 149 version 1. 5 18.3 marking example ? wafer, dice: name rom type device package temperature material s8p27 35 w otp 27 35 wafer - 2 0 ~ 85 - sn8p27 35 h otp 27 35 dice - 20 ~85 - ? green package: name rom type device package temperature material sn8p27 35 pg otp 27 35 p - dip - 20 ~85 green package sn8p27 35f g otp 2735 lqfp - 20 ~85 green package sn8p273 4k g otp 2735 sk - dip - 20 ~85 green package sn8p2734 s g otp 2735 sop - 20 ~85 green package sn8p273 3k g otp 2735 sk - dip - 20 ~85 green package sn8p273 3s g otp 2735 sop - 20 ~85 green package sn8p273 2 pg otp 2735 p - dip - 20 ~85 green package sn8p273 2s g otp 2735 sop - 20 ~85 green package sn8p27 35 pdg otp 27 35 p - dip - 40 ~85 green package sn8p27 35f dg otp 27 35 lqfp - 4 0 ~85 green package sn8p2734k d g otp 2735 sk - dip - 40 ~85 green package sn8p2734s d g otp 2735 sop - 40 ~85 green package SN8P2733k d g otp 2735 sk - dip - 40 ~85 green package SN8P2733s d g otp 2735 sop - 40 ~85 green package sn8p2732p d g otp 2735 p - dip - 40 ~ 85 green package sn8p2732s d g otp 2735 sop - 40 ~85 green package ? pb - free package: name rom type device package temperature material sn8p2735pb otp 2735 p - dip - 20 ~85 pb - free package sn8p2735 f b otp 2735 lqfp - 20 ~85 pb - free package sn8p2734k b otp 2 735 sk - dip - 20 ~85 pb - free package sn8p2734s b otp 2735 sop - 20 ~85 pb - free package SN8P2733k b otp 2735 sk - dip - 20 ~85 pb - free package SN8P2733s b otp 2735 sop - 20 ~85 pb - free package sn8p2732p b otp 2735 p - dip - 20 ~85 pb - free package sn8p2732s b otp 2735 sop - 20 ~85 pb - free package sn8p2735pdb otp 2735 p - dip - 40 ~85 pb - free package sn8p2735 f db otp 2735 lqfp - 40 ~85 pb - free package sn8p2734k d b otp 2735 sk - dip - 40 ~85 pb - free package sn8p2734s d b otp 2735 sop - 40 ~85 pb - free package SN8P2733k d b otp 2735 sk - dip - 40 ~85 pb - free package SN8P2733s d b otp 2735 sop - 40 ~85 pb - free package sn8p2732p d b otp 2735 p - dip - 40 ~85 pb - free package sn8p2732s d b otp 2735 sop - 40 ~85 pb - free package
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 150 version 1. 5 18.4 datecode system x x x x xxxxx year month 1=january 2=february . . . . 9=september a=october b=november c=december sonix internal use day 1=01 2=02 . . . . 9=09 a=10 b=11 . . . . 03= 2003 04= 2004 05= 2005 06= 2006 . . . .
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 151 version 1. 5 1 1 1 9 9 9 package information 19.1 p - dip 32 pin symbols min nor max min nor max (inch) (mm) a - - 0.2 2 0 - - 5.588 a1 0.015 - - 0.381 - - a2 0.1 50 0.155 0. 160 3.81 3.937 4.064 d 1.645 1.650 1.660 41.783 41.91 42.164 e 0. 6 00 bsc 15.24 bsc e1 0.540 0. 545 0. 550 13.716 13.843 13.97 l 0.115 0.130 0.150 2.921 3.302 3.81 b 0. 630 0. 650 0. 670 16.002 16.51 17.018 ? 0 7 15 0 7 15
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 152 version 1. 5 19.2 lqfp 32 pin symbols min nor max min nor max (inch) (mm) a - - 0.063 - - 1.6 a1 0.002 0.004 0.006 0.05 0.1 0.15 a2 0.053 0.055 0.057 1.35 1.4 1.45 c1 0.004 0.005 0.006 0.09 0.125 0.16 d 0.354 bsc 9 bsc d1 0.276 bsc 7 bsc bsc e 0.354 bsc 9 bsc e1 0.276 bsc 7 bsc e 0.031 bsc 0.8 bsc b 0.012 0.015 0.018 0.3 0.375 0.45 l 0.018 0.024 0.030 0.45 0.6 0.75 l1 0.039 ref 1 ref
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 153 version 1. 5 19.3 sk - dip 28 pin symbols min nor max min nor max (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - - 0.381 - - a2 0.114 0.130 0.135 2.896 3.302 3.429 d 1.390 1.390 1.400 35.306 35.306 35.560 e 0.310 7.874 e1 0.283 0.288 0.293 7.188 7.315 7.442 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.330 0.350 0.370 8.382 8.890 9.398 ? 0 7 15 0 7 15
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 154 version 1. 5 19.4 sop 28 pin symbols min nor max min nor max (inch) (mm) a 0.093 0.099 0.104 2.362 2.502 2.642 a1 0.004 0.008 0.012 0.102 0.203 0.305 d 0.697 0.705 0.713 17.704 17.907 18.110 e 0. 291 0.295 0.299 7.391 7.493 7.595 h 0.394 0.407 0.419 10.008 10.325 10.643 l 0.016 0.033 0.050 0.406 0.838 1.270 ? 0 4 8 0 4 8
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 155 version 1. 5 19.5 sk - dip 24 pin symbols min nor max min nor max (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - 0.381 - - a2 0.125 0.130 0.135 3.175 3.302 3.429 d 0.735 0.755 0.775 18.669 19.177 19.685 e 0.30 bsc 7.620 bsc e1 0.253 0.258 0.263 6.426 6.553 6.680 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.335 0.355 0.375 8.509 9.017 9.525 ? 0 7 15 0 7 15
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 156 version 1. 5 19.6 sop 24 pin symbols min nor max min nor max (inch) (mm) a - - 0.069 - - 1.753 a1 0.004 - 0.010 0.102 - 0.254 d 0.612 0.618 0.624 15.545 15.697 15.850 e 0.292 0.296 0.299 7.417 7.518 7.595 h 0.405 0.412 0. 419 10.287 10.465 10.643 l 0.021 0.031 0.041 0.533 0.787 1.041 ? 0 4 8 0 4 8
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 157 version 1. 5 19.7 p - dip 20 pin symbols min nor max min nor max (inch) (mm) a - - 0.210 - - 5.334 a1 0.015 - - 0.381 - - a2 0.125 0.130 0.135 3.175 3.302 3.429 d 0. 980 1.030 1.060 2 4 . 89 2 2 6 . 162 2 6 . 924 e 0.300 7.620 e1 0.245 0.250 0.255 6.223 6.350 6.477 l 0.115 0.130 0.150 2.921 3.302 3.810 b 0.335 0.355 0.375 8.509 9.017 9.525 ? 0 7 15 0 7 15
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 158 version 1. 5 19.8 sop 20 pin symbols min nor max min nor max (inch) (mm) a 0.093 0.099 0.104 2.362 2.502 2.642 a1 0.004 0.008 0.012 0.102 0.203 0.305 d 0.496 0. 502 0.508 12.598 12.751 12.903 e 0.291 0.295 0.299 7.391 7.493 7.595 h 0.394 0.407 0.419 10.008 10.325 10.643 l 0.016 0.033 0.050 0.406 0.838 1.270 ? 0 4 8 0 4 8
sn8p2735 adc, op - amp, comparator 8 - bit micro - controller sonix technology co., ltd page 159 version 1. 5 sonix reserves the right to make change without further notice to any products herein to improve reliability, function or design . sonix does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. sonix products are not designed, intended, or authorized for us as components in systems intended, for surgical implant into the body, or other applications intended to support or sustain life, or for any other a pplication in which the failure of the sonix product could create a situation where personal injury or death may occur. should buyer purchase or use sonix products for any such unintended or unauthorized application. buyer shall indemnify and hold sonix an d its officers , employees, subsidiaries, affiliates and distributors harmless against all claims, cost, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that sonix was negligent regarding the design or manufacture of the part. main office: address: 10f - 1, no.36, taiyuan street, chupei city, hsinchu, taiwan r.o.c. tel: 886 - 3 - 560 0888 fax: 886 - 3 - 560 0889 taipei office: address: 15f - 2, no.171, song ted road, taipei, taiwan r.o.c. tel: 886 - 2 - 2759 1980 fax: 886 - 2 - 2759 8180 hong kong office: unit 1519 , chevalier commercial centre, no.8 wang hoi road , kowloon bay, hong kong. t el : 852 - 2723 - 8086 f ax : 852 - 2723 - 9179 technical support by email : sn8fae@sonix.com.tw

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